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Resilient structure for Big data throughput

IP.com Disclosure Number: IPCOM000240268D
Publication Date: 2015-Jan-20
Document File: 3 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a hardware technique based on hybrid multi-ported memory and multi-valued input/output (I/O) design. This multi-ported and hybrid memory solution increases the bandwidth and data volume for Very Large Scale Integrated (VLSI) circuits.

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Resilient structure for Big data throughput

As big data applications grow, the need to move data on-chip, store, and process at faster rates is becoming increasingly important. While processing performance is rapidly growing, the input/output (I/O) and memory read/write performance is lagging behind. The throughput of memory read/write rates are constrained by the number of available ports. The typical solution to increase ports comes at a significant cost in area and energy.

Current hardware solutions for increasing bandwidth include electronic -Dynamic Random Access Memory (e-DRAM) and storage class memories. Each one has deficiencies. Many of the problems persist as the technology scales. On-chip DRAM may not be offered as a solution for 10nm onward, due to scalability issues. Memory solutions have performance issues compared to Static Random Access Memory (SRAM). Resilient solutions are needed to provide stability, write-ability and performance.

The novel contribution is a hardware technique based on hybrid multi -ported memory and multi-valued I/O design. This multi-ported and hybrid memory solution increases the bandwidth and data volume for Very Large Scale Integrated (VLSI) circuits. Using the hybrid memory banks, L1 and L2 Cache hierarchy can be collapsed. The hybrid can be made of an 8T three-port cell or a 6T cell large cell, while L2 can be made of a smaller 6T cell. This reduces ion interconnects

The solution comprises novel designs for both SRAM storage and chip I /O. The designs are generally useable where bandwidth to memory and I/O considerations are important, and are particularly well suited to areas in which large amounts of tiny data occur (e.g., in the mobile space, with text analysis). Further, when combined with multiple or multi-threaded low-power embedded processors, the computational rate can be matched with memory and I/O rates.

The desig...