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A Dual Edge Sequential Architecture for Eliminating the Hold Requirement from the Test Path

IP.com Disclosure Number: IPCOM000240310D
Publication Date: 2015-Jan-21
Document File: 5 page(s) / 904K

Publishing Venue

The IP.com Prior Art Database

Abstract

Scannability has always been a challenge and with complex architectures, the challenges increase by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan architectures and complex scan-shift methodology. In this paper we propose a dual edge flip-flop architecture designed to eradicate HOLD fixing by removing the HOLD violations completely in the design. The proposed architecture helps reduce the number of HOLD elements in the scan path to zero, which otherwise continue to eat unnecessary power/area/routing resources throughout the SoC life cycle after one time testing plus a very ROBUST and easy solution from the scan-DFT methodology perspective. The proposed architecture is a zero HOLD architecture as far as the test path is concerned and a correct by constructs mechanism for the robust scan methodology.

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A Dual Edge Sequential Architecture for Eliminating the Hold Requirement from the Test Path

Scannability has always been a challenge and with complex architectures, the challenges increase by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan architectures and complex scan-shift methodology.  In this paper we propose a dual edge flip-flop architecture designed to eradicate HOLD fixing by removing the HOLD violations completely in the design.  The proposed architecture helps reduce the number of HOLD elements in the scan path to zero, which otherwise continue to eat unnecessary power/area/routing resources throughout the SoC life cycle after one time testing plus a very ROBUST and easy solution from the scan-DFT methodology perspective.  The proposed architecture is a zero HOLD architecture as far as the test path is concerned and a correct by constructs mechanismfor the robust scan methodology.

Fig.1 is a conventional dual edge Flip-Flop architecture.

Fig. 1 - Conventional Dual Edge Flip Flop

The conventional dual edge flip-flop architecture is a normal dual edge mode of operation in the functional mode as well as in the scan mode. One of the most prevalent hold violations occurs when there is no combinational logic between any two flip-flops. This can be seen very frequently in scan chains.  In order to resolve the hold violation either an extra delay is introduced between the two flops or the clock skew must be reduced.  So, usage of the conventional flip-flop introduces a lot of hold violations in the test/scan path and these need to be fixed, which requires using lot of hold buffers, which ultimately leads to a waste of area/time/power and still is susceptible to hold failures when in silicon.  The proposed architecture fixes the hold violations by inserting a half-cycle clock cycle delay by the virtue of design in the scan path i.e. for the SI pin without impacting anything else.

Fig. 2 is our proposed dual edge Flip-Flop architecture.

Fig. 2 Block Diagram of the propose...