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System and Method for Efficient Memory Expansion

IP.com Disclosure Number: IPCOM000240341D
Publication Date: 2015-Jan-23
Document File: 8 page(s) / 931K

Publishing Venue

The IP.com Prior Art Database

Abstract

In a System-on-Chip (SoC), the access to flash memories is accomplished through Flash Memory Controller Modules. A Flash Memory Controller Module typically follows multiple chip-selects based approach to access multiple devices using shared address, data and control buses. This paper describes an efficient method to interface NOR flash memories with such flash controllers.

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System and Method for Efficient Memory Expansion

Abstract

In a System-on-Chip (SoC), the access to flash memories is accomplished through Flash Memory Controller Modules. A Flash Memory Controller Module typically follows multiple chip-selects based approach to access multiple devices using shared address, data and control buses. This paper describes an efficient method to interface NOR flash memories with such flash controllers.

Introduction

Flash Memory Controller Modules are used in SoCs to control access from system bus masters such as CPUs, GPUs or DMAs to external memories such as NOR Flash. The maximum capacity of NOR flash which can be connected to a particular flash controller depends on the number of address lines provided by that controller. Many times embedded system designers need to have a flash memory in the system which is bigger than what is supported by flash controller. In such cases the obvious solution is, interface two flash devices to two separate chip-selects. This approach has drawbacks. Technique mentioned in this paper facilitates increasing flash memory space by using a single bigger capacity NOR flash instead of two NOR flashes. 

Problem Description

Fig. 1 shows a typical scheme of interfacing NOR flash with SoC’s flash controller. Flash controller has two chip-select (CS) signals. One of the CS has been utilized to connect a NOR flash of 2n byte capacity where n is the number of address lines provided by flash controller.

If it is required to increase (double) the flash capacity the obvious solution (or conventional solution) is to interface another flash on CS1. This scheme has been shown in fig. 2.

This solution comes with penalties. It occupies more board space because two separate flash chips are required to be mounted on board. Power consumption of overall system increases because of an added component. It also increases loading on flash controller IOs which in turn effects rise/fall times of signals. Board routing gets complicated because all the shared signals (address, data and control) are required to be routed to both the flash devices. The scheme obviously increases bill of material (BOM) cost. It also adds to software complexity.

Solution

The penalties mentioned above can be mitigated if instead of using two NOR flash devices only one device of higher capacity is used. The problem with uing a single device is un-availability of extra address lines. Fig. 3 depicts the situation. NOR flash device has n+1 address lines whereas flash controller provides only n address lines. So there is one additional address line available in NOR flash device that doesn’t have corresponding address line from flash controller.

This problem can solved if an additional address line can be generated using the unused additional CS (which is CS1). Fig. 4 shows the solution.

In this solution, on-board...