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EEPROM EMULATION USING INTERNAL FLASH MEMORY

IP.com Disclosure Number: IPCOM000240368D
Publication Date: 2015-Jan-27
Document File: 9 page(s) / 167K

Publishing Venue

The IP.com Prior Art Database

Abstract

A microcontroller or system-on-a-chip (SOC) can emulate an EEPROM using the internal flash memory of the system. The system can implement a translation layer and a corresponding algorithm that uses a circular buffer in flash and keeps track of the indices of the buffer. The design can provide the benefit of enhanced apparent endurance and byte addressability provided by conventional EEPROMs. The translation algorithm can implement one or more of the following features: easy to use interfaces, automatic wear leveling, configurable EEPROM size, easy portability to other devices.

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eeprom emulation using internal flash memory

Background

Some microcontroller systems store nonvolatile data using internal flash memory or using an external EEPROM chip.  Using internal flash memory can have some disadvantages.  For example, the endurance of internal flash may be only 1/10th of that of EEPROM. This can limit the usability of internal flash when the required write cycles are more than 10,000.  In some cases, the internal flash is not byte addressable.  To write to the internal flash memory, an entire block has to be erased prior to writing new data, which can make the use of internal flash cumbersome.  In some cases, the user cannot extend the endurance of internal flash.  Using EEPROM can have some disadvantages too.  For example, in some systems, the user cannot increase the size or endurance of an EEPROM chip.  In some systems the EEPROM is an external part, which can lead to more cost, more space, more power consumption and also using more pins of the controller for interface.

keywords

Microcontroller, system-on-a-chip (SOC), flash memory, EEPROM, nonvolatile storage, memory endurance, byte addressability, wear leveling, translation layer, circular buffer. 

Summary

A microcontroller or system-on-a-chip (SOC) can emulate an EEPROM using the internal flash memory of the system.  The system can implement a translation layer and a corresponding algorithm that uses a circular buffer in flash and keeps track of the indices of the buffer.  The design can provide the benefit of enhanced apparent endurance and byte addressability provided by conventional EEPROMs. The translation algorithm can implement one or more of the following features: easy to use interfaces, automatic wear leveling, configurable EEPROM size, easy portability to other devices.

The design can eliminate or reduce the need for external nonvolatile storage when working with microcontrollers that lack an internal nonvolatile storage.  The design emulates an EEPROM using internal flash of these microcontrollers with respect to usability and endurance. The design can also let the user trade between endurance and size, which is a feature not typically provided by nonvolatile storage.

The design can solve the endurance issues typically associated with flash. Using this approach the apparent endurance can be made, e.g., 64x of flash endurance, thereby exceeding some EEPROMs. The design can replace an external EEPROM in various systems.  The translation layer can also simplify issues in programming the system.  The interfaces exposed by this design can be similar to the ones used by conventional EEPROMs. The software overhead for replacing external EEPROMs with emulated EEPROM can be very low.  Using fewer external parts can mean less cost, less space, less consumption and free up pins for other peripherals.

Description

Introduction

Some embedded systems rely on nonvolatile parameters that are preserved across reset or power-loss events. In some systems th...