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A Method and System for Designing Buffer FET for Minimizing Self-Heating

IP.com Disclosure Number: IPCOM000240378D
Publication Date: 2015-Jan-28
Document File: 5 page(s) / 197K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for minimizing self-heating problem in large Field-effect transistors (FETs) such as, multi-finger buffer FETs and large inverters by segmenting and interleaving between different circuit stages.

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A Method and System for Designing Buffer FET for Minimizing Self -

-Heating

Heating

Disclosed is a method and system for minimizing self-heating problem in large

Field-effect transistors (FETs) such as, multi-finger buffer FETs and large inverters by segmenting and interleaving between different circuit stages.

In accordance with the method and system, the buffer FET is designed by segmenting 1st stage (input) and 2nd stage (driver) inverters. Thereafter, intercalating the inventers in such a way that reduces overall thermal resistance in the 2nd stage. The method and system can be used in a verity of circuits such as, but not limited to, planar-soi, soi-FinFETs, bulk-planar, bulk-FinFETs, and nanowires.

Fig. 1 illustrates a distributed 1st-stage (input) inside a segmented-2nd-stage FET.

Figure 1

The 2nd stage (driver stage) is segmented into multiple sections and distributed over larger area to reduce the overall thermal resistance of the driver stage , as illustrated in the fig. 1.

Figure 2 illustrates an exemplary embodiment of the disclosed method .

1


Page 02 of 5

Figure 2

Following is the algorithm for implementation of the exemplary method :
Step 1) N_segments = ceil( Nfin2nd / N_crit) where 'ceil' is the ceiling function (e.g. ceil(2.3) = 3)

Step 2) Divide the 2nd stage into N_segments number of segments (round off if not a

whole number. A designer can decide)

Step 3) Divide the 1st stage into (N_segments-1) number of segments (round off if not a whole num...