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A New Metal Gate Recess Scheme for RMG Gate Resistance Reduction

IP.com Disclosure Number: IPCOM000240427D
Publication Date: 2015-Jan-29
Document File: 4 page(s) / 193K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to introduce an additional mask as a means of protecting the long channel for a negative Field Effect Transistor (nFET) first scheme. The approach is to perform the gate recess at the Tungsten (W) level, instead of at Tungsten Hexafluoride (WF) metal deposition.

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A New Metal Gate Recess Scheme for RMG Gate Resistance Reduction

Without work function metal (WFM) recess, the gate resistance of 14 nm Silicon on Insulator (SOI) is very high. Even if the clustering stack is used, the projected gate resistance is still higher than the current target resistance (23.3 ohm/sq.). Although WFM recess is introduced to reduce the gate resistance, the scheme is complicated.

The novel contribution is the introduction of an additional mask to protect the long channel for a negative Field Effect Transistor (nFET) first scheme. The gate recess is done at Tungsten (W) level, instead of at Tungsten Hexafluoride (WF) metal deposition. This is a simpler scheme than a WFM recess at WF metal deposition is. This approach removes the need for an additional mask, reduces gate resistance, and lowers costs.

The following figures represent the components and process for implementing the new metal gate recess scheme to reduce replacement metal gate (RMG) resistance.

Figure 1: Gate Stack Scheme (nFET first pattern generation (PG) patterning)

Figure 2: Step 1: nFET first PG patterning and post WF metal deposition

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Figure 3: Step 2: Gate W deposition

Figure 4: Step 3: W planarization Chemical-Mechanical Planarization (CMP)

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Figure 5: Step 4: W Gate recess

Figure 6: Step 5: WFM recess

Figure 7: Step 6, Option 1: Fluorine Free Tungsten (FFW) + LynxW Deposition

Figure 8: Step 6, Option 2: Thin wetting Titanium Nitride (TiN) + conv...