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Method of forming anti-fuse structure in Interconnects

IP.com Disclosure Number: IPCOM000240435D
Publication Date: 2015-Jan-29
Document File: 3 page(s) / 213K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel method for forming semiconductor fuse structures using two fuse structure designs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 95% of the total text.

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Method of forming anti-fuse structure in Interconnects

Back End of Line (BEOL) interconnect fuses (i.e. anti-fuses) are becoming important devices as technology scales and Front End of Line (FEOL) fuses become more challenging.

Traditional BEOL fuses based on via structures rely on copper corrosion, hollow metal, and misaligned vias, which present challenges of metal fill and an additional fuse photo-layer. The use of electro-migration fails or resistance fails often requires additional mask levels and highly optimized integration to control the metallization process for fuses.

The solution proposes two unique fuse structure designs. The first is a misaligned self-aligned via (SAV) in the non-critical non-SAV direction, coupled with a wet etch of copper (Cu), which leads to high via resistance; this can be electromagnetically (EM) induced to fail. The second is a lateral copper etch of line below the large non-SAV bottom, which leads to high via resistance. These unique fuse structures are based on a misaligned or larger than nominal via size design and wet etch that produces high ISO-VIA resistance, which can fail at higher stress current/voltage. This fuse design requires no additional mask levels and can implement two different types of fuses, which aids designers.

Figure 1: Process flow (1 of 2)

Figure 2: Process flow (2 of 2)

Figure 3: V2 ISOVIA Transmission Electron Microscopy (TEM) with high Rc(700~1200ohm)

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Figure 4: V2 ISOVIA Physical Fail...