Browse Prior Art Database

SUPPRESSING CIRCUIT TO PROTECT GATE DRIVER IC

IP.com Disclosure Number: IPCOM000240469D
Publication Date: 2015-Feb-02
Document File: 8 page(s) / 272K

Publishing Venue

The IP.com Prior Art Database

Abstract

A half-bridge circuit with stray inductances is presented. Embodiments of the present invention contain a suppressing circuit that effectively dampens Vs undershoot, preventing damage to the half bridge gate driver IC due to Vs undershoot, generally making the system safer.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 42% of the total text.

Page 01 of 8

253444

SUPPRESSING CIRCUIT TO PROTECT GATE DRIVER IC

BACKGROUND OF THE INVENTION

      Embodiments of the invention relate to electronics-containing devices and more specifically, to electronic circuits.

      Electronic circuits require that current flow in an organized manner to be enabled to reach all of the components. Of the problems caused by parasitic devices, one of the main issues for control half-bridge gate drivers (IC) is a tendency for the high-side floating supply offset voltage (Vs) to undershoot the ground following switching events. Of the high voltage ICs in the market, absolute minimum undershoot is -25.3V. In some cases, this negative spike cannot be controlled within the safe range by means of layout optimization.

      One of these cases is an induction cooktop application. Pan removal at a lower frequency will result in the IC damage due to the voltage undershot of Vs. As illustrated in Figure 1, when the pan is removed, the upper insulated-gate bipolar transistor (IGBT) shuts down, forcing inductive current to commutate along the inductor Ls2 and a diode D2. Thus there is an instant voltage drop on Ls2, which conduces to undershoot the ground. Further, Ls2 and snubber capacitor Cn2 form an oscillation loop. Similarly, inductor Ls1 and diode D1 lead to overshoot the upper power when the lower IGBT switches off. For the case of pan removal, only undershoot is important.

      In some extreme cases, such as pan removal in the application of an induction cooktop, the level of undershoot is still considered too high even with the combination of minimizing stray inductance at source by layout optimization, adding external snubbing and/or increasing gate drive resistance and fast anti-parallel clamping diodes. Thus it is desirable to provide a safe and efficient way to minimize Vs undershoot in the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

      Reference is made to the accompanying drawings in which an exemplary embodiment of the invention is illustrated as described in more detail in the description below, in which:

      Figure 1 illustrates a typical embodiment of a half-bridge circuit with stray inductances.


Page 02 of 8

253444

Figure 2 is a graphical representation of a Vs waveform in simulation.

Figure 3 is a graphical representation of a Vs waveform in experiment.

      Figure 4 illustrates an exemplary embodiment of a suppressing circuit to protect gate driver IC.

      Figure 5 is a graphical representation of the waveforms of Vs, VB, Vph, and coil current with a Vs restrained circuit.

      Figure 6 is a graphical representation of the VS waveform of Vs without a suppressing circuit.

DETAILED DESCRIPTION OF THE INVENTION

      The following description of exemplary embodiments relates to a suppressing circuit and refers to the accompanying drawings. The present invention provides a way to effectively dampen Vs undershoot, preventing damage to the half bridge gate driver IC.


Page 03 of 8

253444

VDD

DBS

VB

HO

VS

VDD

LO

COM

Q1

CBS

D1

Cn1

Ls1

Lload

Rload HV1 HV2

Q...