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PROGRAMMABLE LOGIC AND PERIPHERAL INTERCONNECTS IN CONTROLLERS PRIMARILY FOR SUBSEA APPLICATIONS

IP.com Disclosure Number: IPCOM000240473D
Publication Date: 2015-Feb-03
Document File: 3 page(s) / 101K

Publishing Venue

The IP.com Prior Art Database

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PROGRAMMABLE LOGIC AND PERIPHERAL INTERCONNECTS IN CONTROLLERS

PRIMARILY FOR SUBSEA APPLICATIONS

BACKGROUND


This disclosure is related to the design of Subsea Controllers found within Subsea Electronic Modules (SEM).

Typical SEM Controllers are designed with a custom or special purpose (e.g. automotive) CPU or MCU at its core. Due to limitations in regard to the amount of peripheral interfaces within the CPU / MCU, peripheral components such as ADC's and DAC's are connected via serial busses in a daisy chain manner to the CPU / MCU.

This bears the potential risk of a single failing peripheral component to compromise all components on the bus and as a consequence all of the SEM Controller functionality.

As Subsea applications aim for the highest possible reliability, a change to the architectural design of the electronics is proposed to achieve an overall higher reliability.

Bus type architectures in regard to interconnecting peripheral components in an electrical design, pose the threat of compromising the complete Controller functionality.

STATEMENT OF PROBLEM


Classical SEM Controllers use CPU's or MCU's as the controller of choice at their core. Such components usually have a limited amount of peripheral interconnect interfaces, forcing the designer to use a bus type topology when connecting peripheral components such as ADC's and DAC's to the central unit.

The use of a programmable logic components (e.g. FPGA's) as a central unit, allows to replicate the number of peripheral interconnect interfaces for every single ADC or DAC which is in the design of the SEM controller. This in return allows to connect all peripheral components in a star type topology.

In a star type topology, a single peripheral component can fail and will not affect the remaining components, as they do not share a common interface system like in the bus type topology.

Therefore, this invention focuses on increasing the overall reliability of a SEM controller.

THE INVENTION

     Figure 1 below shows the typical design of interconnecting peripheral components in a SEM controller. The peripheral components (2, 3, 4) are connected in a bus type fashion to a single peripheral interconnect...