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Buried Source Drain Stressor

IP.com Disclosure Number: IPCOM000240486D
Publication Date: 2015-Feb-03
Document File: 3 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use a buried stressor to decouple the requirements of electrical and physical properties of a material. Separating the physical and electrical source drain materials addresses any conflicts created between stressor material requirements and electrical requirements in a device.

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Buried Source Drain Stressor

The requirement for a physical stress in a device is important ; however, it can conflict

with the electrical requirement for a source drain (S/D). Even with advanced devices such as FIN Field Effect Transistors (FINFET), high mobility channels such as Silicon Germanium (SiGe), III-V, some stressor is still needed. The stressor material requirement sometimes conflicts with the electrical requirement . For example, large lattice is desired for compressive stress, but a smaller band gap that goes with the material is not, because it introduces leakage.

The solution is to separate the physical and electrical source drain materials . The novel contribution is a method to use a buried stressor to decouple the requirements of electrical and physical properties of a material.

This is applicable for planar/FIN/three-dimensional (3D) devices and bulk or Semiconductor on Insulator (SOI).

As shown in Figure 1, the device layer can be SiGe with 85% Ge. The device can be FINFET or Planar.

Figure 1: Device layers

Figures 2-7 illustrate the implementation of the solution .

Figure 2: Form isolation such as Shallow Trench Isolation (STI)

Figure 3: Form gate and spacer

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Figure 4: Form recessed source drain (S/D)

Figure 5: Deposition of S/D material

As shown in Figure 5, the device layer can be SiGe with 85% Ge. The epitaxy (epi) material can be a material that has a very large lattice delta to device layer (e.g., Indium Phosphorous (InP)...