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Circuit to mask failure due to extra memory bits

IP.com Disclosure Number: IPCOM000240492D
Publication Date: 2015-Feb-03
Document File: 3 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes a circuit that masks failures caused by extra memory bits during memory built in self-test (MBIST).

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Circuit to mask failure due to extra memory bits

Introduction

This document describes a circuit that masks failures caused by extra memory bits during memory built in self-test (MBIST).

Problem Statement

At times due to memory compiler/design limitation, we end up with memories of larger sizes (address size or word length) than what is functionally required.  These extra memory bit are not accessed during functional mode operations, and often are tied to static values in case of extra word length, or never accessed in case of extra address.  However, during MBIST these extra memory bits are accessed, and faults on these bit are taken as valid memory faults, which can reduce yield.

Proposed Design

We propose a circuit to avoid the yield loss due to failure of the extra memory bits without compromising test quality.  A circuit that is active during MBIST mode masks the failure reported on extra word length and address size.

The proposed circuit requires changes in the following BIST components:

q  Mask Generator -

•       Address Comparator - Compares current address with the “last address to test” based on memory under test

•       BIT Mask Gen - Making data generator which takes into account memory word length.

Most MBIST comparators already come with a bit masking logic, which allows them to test memories of different sizes (in this they generate masking data based on memory size, so that comparator only works for the selected memory size, here BIST also generates data only f...