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Browse Prior Art Database

Self Gated Clock Gate

IP.com Disclosure Number: IPCOM000240494D
Publication Date: 2015-Feb-03
Document File: 4 page(s) / 550K

Publishing Venue

The IP.com Prior Art Database

Abstract

A clock gating cell for gating clock signal includes a clock gating stage and an output latch stage. Functionally when clock gating enable is high, output clock is gated. The clock gating stage controls the clock reaching the output latch stage, based on latch output and clock gating enable signal, thus saving internal power consumption of clock gating cell.

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Self Gated Clock Gate

Abstract

A clock gating cell for gating clock signal includes a clock gating stage and an output latch stage. Functionally when clock gating enable is high, output clock is gated. The clock gating stage controls the clock reaching the output latch stage, based on latch output and clock gating enable signal, thus saving internal power consumption of clock gating cell.

Background

Clock power consumes 40-50 percent of total chip power and is expected to significantly increase with increasing demands of high performance and hence high frequency chips. Clock gating cells help in dynamic power reduction by gating clock signals going to sequential elements in idle mode using an enable signal. Since some additional logic is added to the design for clock gating, power savings achieved from using clock gating cells is somewhat reduced because of power consumption of the clock gating cell itself.

Integrated Clock Gating Cell

Integrated clock gating cells are very commonly used in designs to gate clock signals. It is typically implemented using a latch, which synchronizes the clock gating enable (E) signal with the clock (CK) to avoid any glitch in output gated clock (GCK), and an AND gate to provide gated clock output as shown in Fig. 1. Functionally when enable (E) is low, output clock is gated thus saving on dynamic power consumption. But the internal transistors of clock gating cell which are operating on un-gated clock (CK) are still switching, because of which internal power consumption of clock gate itself is very high thus somewhat reducing the power saving achieved with the use of clock gating cell. From Fig. 1 we can see that total number of transistors in a typical clock gate is 20 whereas, number of transistors working at clock frequency are 10. So in a typical clock gate 50% of the transistors are still switching even when enable (E) goes low and hence contributing to internal power consumption.

Proposed Clock Gate Circuit

The proposed clock gate circuit is shown in Fig. 2. The clock gate can be viewed as 2 stage circuit having (a) clock gating stage which generated CPI and CPN clock signals, and (b) output stage, which uses these signals to provide clock gate output Q. The clock gating stage is modified in comparison to the conventional clock gate to achieve power savings when the clock gate is disabled (i.e., E is low). The proposed circuit functionality is reverse with respect to the conventional clock gate in the sense that output clock (Q) is gated when E is high and clock is passed when E is low. To achieve power saving, latch output (LOP) and clock gating enable (E) are used in clock gating stage to provide gated clock to output stage when enable is high (output clock needs to be gated) as shown in Fig. 2.  From the figure we can see that total number of transistors in the proposed...