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Method and System for Utilizing Multi Master High Speed Interface to Use I2C Bus Bandwidth

IP.com Disclosure Number: IPCOM000240497D
Publication Date: 2015-Feb-03
Document File: 1 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for utilizing multi master high speed interface to use I2C bus bandwidth.

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Method and System for Utilizing Multi Master High Speed Interface to Use I2C Bus Bandwidth

As Printed Circuit Boards (PCBs) become more and more congested with signals it is important to try and minimize the number of interfaces. The variety of interfaces varies significantly from very low speed to ultra-high speed. By combining multiple interfaces over one set of signals it is possible to help alleviate some of the congestion. I2C bus can be used for this. The unused bandwidth can be easily converted into a high speed bus for use between FPGAs and/or CPLDs by simply overlaying a single master high speed interface into the unused bandwidth spaces. So, there is a need for a high speed multi master interface to overlay that utilizes unused bandwidth at a much higher speeds.

Disclosed is a method and system for utilizing multi master high speed interface to use I2C bus bandwidth. The method and system implements a multi-master solution which allows multiple master interface to be able to use the idle I2C bus bandwidth.

As illustrated in the Figure, multi-master interface works in four phases such as, master discovery, master grant, master data transaction, and master termination.

Figure

Thus, the method and system utilizes multi master high speed interface for conserving I2C bus bandwidth.

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