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I2C Bus with Accelerated Data Transfer Phase

IP.com Disclosure Number: IPCOM000240499D
Publication Date: 2015-Feb-03
Document File: 6 page(s) / 256K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for including a high-speed data transfer cycle inside the Inter-Integrated Circuit (I2C) legitimate transactions for transferring large amounts of data from one bus master to a bus slave within a short amount of time and without adding anything new to the physical design.

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I2C Bus with Accelerated Data Transfer Phase

As Printed Circuit Boards (PCBs) become increasingly congested with signals, it is important to minimize the number of interfaces.

The present disclosure describes a novel solution for including a high-speed data transfer cycle inside the Inter-Integrated Circuit (I2C) legitimate transactions for transferring large amounts of data from one bus master to a bus slave within a short amount of time and without adding anything new to the physical design.

Combining a high-speed interface and defining a custom protocol over one set of I2C signals alleviates some of the congestion. It saves cost by fitting into smaller Field Programmable Gate Array (FPGA)/Complex Programmable Logic Device (CPLD) devices (fewer pins needed), as well as having less routing on a PCB. The I2C bus can be used for this. The high-speed data transfer does not modify the I2C protocol and permits large transfers in the time allotted for I2C normal operation.

I2C normally runs up to 100 to 400 KHz, reaching 3.4MHz in high-speed mode (not usual for I2C). This is quite slow in today's electronics. I2C is mainly used as a low speed management channel to provide information to a master device. There is a lot of bandwidth wasted. This unused bandwidth can be used as a high-speed signaling bus between programmable devices such as CPLDs or FPGAs. The speed of this bus is directly proportional to the amount of interfaces on the I2C bus. When only a few devices are on the bus, the FPGAs/CPLDs can easily use the unused bandwidth to overlay a high-speed multi-megabit per second interface on it, within a normal I2C operation cycle.

Operation Principles

1. START/STOP Commands (Figure 1): These two I2C commands are determined by the Serial Data (SDA)/Serial Clock (SCL) levels and time relationship, as in the figure below. A master always controls the START/STOP for the transaction cycle. A slave device responds to the master device's commands as per the datagram below.

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Figure 1: START/STOP Commands


2. I2C Data Transfer Cycles (normal) (Figures 2-5)

Figure 2: Data transfer on I2C bus

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Figure 3: A master-transmitter addressing a slave receiver with a 7-bit address (the transfer direction is not changed)

Figure 4: A master reads a slave immediately after the first byte

Figure 5: Combined format

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The address phase is followed by an acknowledge phase responded by the slave device. It is after the ACK phase that the high-speed transaction initiated by the master can begin. Its steps are (inside the I2C operation):


• Master addresses a slave by physical address, orders Read/Write (R/W) operatio...