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System and Method for Composite Response in the Presence of Local-Layout Effects

IP.com Disclosure Number: IPCOM000240519D
Publication Date: 2015-Feb-05
Document File: 3 page(s) / 60K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a methodology that analyzes the impact of Local Layout Effect (LLE) on a given set of performance-reference circuits to develop overrides for improved accuracy in product performance and leakage prediction.

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System and Method for Composite Response in the Presence of Local-Layout Effects

Local Layout Effect (LLE) reference levels for Simulation Program with Integrated Circuit Emphasis (SPICE) models are based on single Field Effect Transistor (FET) layouts. A set of performance-reference circuits, however, contains many transistors and therefore the conventional, single-FET definition of an LLE reference layout is not directly compatible with a set of performance-reference circuits. At the same

time, circuit designers want the predicted performance and leakage of a set of performance-reference circuits to accurately reflect LLE, without having to calculate

the LLE of each and every FET.

A method is needed to develop LLE overrides for circuit simulation that accurately

capture the average LLE of the set of performance-reference circuits, and thus accurately predict product performance and leakage.

The novel contribution is a methodology in which the impact of LLE on each FET in a set of performance-reference circuits is analyzed, in order to match the average delay and leakage of the set as predicted with overrides to the prediction with FET-specific LLE. The system and method include the LLE influence of both N-type and P-type metal-oxide semiconductor (Nmos and Pmos) transistors. The overrides can be scaled for temperature, power supply, and skew corner.

The implementation procedure follows:

1. Simulate the full netlists with LLE turned on for both Nmos and Pmos an...