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Timing Optimization Method using Wiring Modifications for Chips using Multi-Patterning

IP.com Disclosure Number: IPCOM000240520D
Publication Date: 2015-Feb-05
Document File: 2 page(s) / 70K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to optimize the layout of double patterned metal wiring. This includes a method to optimize the delay variation of paths to meet the timing requirements of paths without area or dynamic/leakage power overhead.

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Timing Optimization Method using Wiring Modifications for Chips using Multi-Patterning

Multi-patterning employs consecutive steps of Litho-Etch (LE) with a set of masks to

fabricate patterns on chips. For example, double patterning uses two masks with two steps, LELE. The delay variation of Back End of Line (BEOL) metal wires fabricated by different masks is different with certain amount of correlation between the components. The overall delay variation along a wire is therefore a combination of the variation components contributed by multi-patterned wires.

A method is needed to use this relationship to optimize timing.

Figure 1: Current net patterns/relationships

The novel contribution is a method to optimize the layout of double patterned metal

wiring. This includes a method to optimize the delay variation of paths to meet the timing requirements of paths without area or dynamic/leakage power overhead. The method introduces double patterned wires in a "mix n match" format along a timing path in such a way that delay variation can be increased under certain conditions and can be decreased in some other to meet timing requirements.

This method for optimizing a wiring layout of an integrated circuit for timing benefit begins with a timing analysis performed on an input routed netlist using a multimodal characterization of colored nets fabricated using separate masks. The method then analyzes the routed design and determines the cumulative delay variation along a timing path comprises of said nets. The wiring layout of the said timing path is then optimized such that variation of the delay can be optimized to meet certain timing requirements.

The method includes definitions of correlation parameters between wires that are fabricated using the same mask as well as a correlation between wires fabricated using separate masks. The wiring layout for timing the critical path is analyzed for coloring distribution post-determination of delay variation along the path. The late mode critical ti...