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A Method for Reducing Burn-In Induced BTI Shifting

IP.com Disclosure Number: IPCOM000240521D
Publication Date: 2015-Feb-05
Document File: 4 page(s) / 261K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reducing or eliminating threshold voltage shifts caused by bias temperature instability (BTI). Also disclosed is an efficient method of practical application of Low Bias Bake (LBB) to reduce or eliminate threshold voltage shifts caused by BTI as the result of burn-in (BI).

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A Method for Reducing Burn-In Induced BTI Shifting

During the burn-in (BI) process, Bias Temperature Instability (BTI) causes Threshold

Voltage shifts within the transistors of Complementary Metal-Oxide Semiconductor (CMOS) chip designs. Multiple issues, problems, and implications result from this Vt shifting:

• Parts are inherently slower coming out of the BI process • Parts have additional performance variability when exiting the BI process • Parts exit the BI process with some degree of "useful life" degradation
• An additional performance guard band is needed to cover worst-case shifting

Voltage (Vt) shifting needs to be prevented to as high a degree as is possible. Practically, complete prevention of Vt shifting is not possible; therefore, the goal is to reduce BTI shifting.

Past solutions include a very high temperature (no bias) bakeout process to partially reset BTI shifts after BI. This was only possible on ceramic packages and is not possible on organic packages due to materials' maximum temperature limitations (organic and lead-free solder). Some work has been suggested and implemented related to pattern based shifting. The pattern solutions are directed at the prevention of asymmetrical shifting (some devices shifting more than others do). Some work has been investigated and published related to materials and silicon fabrication and processing to reduce BTI effects. These efforts are aimed at reducing the susceptibility to Vt shifts that occur either in burn-in or in the field. These are typically transistor and silicon fabrication recipes consisting of materials and processing steps/parameters.

In regard to BTI reset/relaxation methods, BTI shifting can be reset to a significant degree with an unbiased high temperature bake (i.e. +350C, 5 min.). The degree of BTI relaxation is a function of temperature and time. Sensitivity to BTI shifting in microprocessors is to the first order a logic sensitivity as the performance critical timing paths are primarily in the logic. In addition, the arrays are typically run at some lesser clock frequency than the logic.

A method is needed to reduce voltage threshold shifting due to burn-in.

The novel idea is to perform a low bias bake as part of the BI stress process to reduce the shifting. The approach utilizes a new type of BTI relaxation consisting of a low voltage, high temperature relaxation. This designated as a Low Bias Bake (LBB). Data collected supports that a BTI-induced shifting can be partially relaxed

with this method.

The method segments the burn-in process to allow the BTI-sensitive critical performance paths i...