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Method and System for Providing Priority Routing of Stitch-through Critical Paths in Three-Dimensional Integrated Circuits

IP.com Disclosure Number: IPCOM000240522D
Publication Date: 2015-Feb-05
Document File: 3 page(s) / 211K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for providing priority routing of stitch-through critical paths in three-dimensional (3D) integrated circuits (ICs).

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Method and System for Providing Priority Routing of Stitch-through Critical Paths in Three-Dimensional Integrated Circuits

Three-dimensional (3D) integrated circuit (IC) contains multiple dies communicating

with each other using through-silicon vias (TSVs) and interconnects. A latch placed

on die 1 of an IC communicates to a memory unit on die 5 of the IC. Interconnects at each die level passes through a metal stack of the die and connects to a micro bump to connect to the TSV in the next die. This process repeats at every die. If priority is not provided to timing critical paths, these potentially long wiring paths at each die level can create timing issues at later stages post detailed wiring.

Accordingly, there is need of a method for prioritizing routing of critical paths to create a direct point to point vertical route for timing critical path components.

Disclosed is a method and system for providing priority routing of stitch-through critical paths in 3D ICs. The method and system aligns cells between dies and forms a vertical feed through for creating shortest routes in 3D space for critical paths. The cells of critical paths are vertically aligned in 3D space during initial placement of cells in 3D ICs. Vertical alignment of cells then reserves vertical

routing channels for stacking vias and prioritizes routing of the critical paths to create a direct point to point vertical route for timing critical path components.

In accordance with the method and sy...