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Yield Optimized Routing

IP.com Disclosure Number: IPCOM000240523D
Publication Date: 2015-Feb-05
Document File: 2 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a yield/reliability improvement routing protocol that builds on known routing protocols.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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Yield Optimized Routing

Semiconductor product testing uses patterns/vectors to ensure that nets meet timing requirements. Critical timing nets apply tighter test requirements than non-critical nets. Test fallout for defects is higher on critical nets; tighter timing leads to a greater probability of fail for an equal number of devices. In addition, the reliability impact of defects on tightly timed nets is higher. Yield routing requirements are applied the same for die level wiring. Yield can be optimized if critical nets are held to a higher yield standard than less critical nets. Reliability is also improved by holding critical nets to more stringent requirements. Requiring all nets to meet the higher standard is not practical because of area/die size impacts.

The method described below increases yield (i.e. reduce test fallout) during semiconductor product testing and improves reliability in system applications.

The novel contribution is a yield/reliability routing protocol that builds on known routing protocols. Different protocol can be assigned to a net. Both critical and less critical nets are identified for the product in this protocol. As shown in Figure 1 and Figure 2, during routing and timing of the semiconductor product, yield/reliability optimized routing is used for critical nets. The method applies less yield optimized
(i.e. uses less area) routing to less critical nets.

Figure 1: Basic idea

Figure 2: Basic idea, cont'd.

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