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Multicore Master Register Configuration

IP.com Disclosure Number: IPCOM000240579D
Publication Date: 2015-Feb-10
Document File: 4 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

When dealing with multicore and heterogeneous systems is not trivial to see the cores allocation and to make their management. The Multicore Master Register Configuration (MMRC) is a feature (hardware and software solution) that can be used for making a dynamic management of the cores of a processor in a heterogeneous (software and/or hardware) multicore system. The current solutions are limited by the fact that they don’t make it easy for the user/OS to manage the applications that need a specific set of cores. Using the Multicore Master Register Configuration makes the programmer’s life easier to write parallel embedded code, letting him to allocate statically or dynamically the core resources, knowing at every step easily what applications are running on what cores. Also, this can be useful for debugging, tracing and in running co-existing operating systems and/or single thread baremetal applications in a multicore embedded environment.

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Multicore Master Register Configuration

Abstract

When dealing with multicore and heterogeneous systems is not trivial to see the cores allocation and to make their management. The Multicore Master Register Configuration (MMRC) is a feature (hardware and software solution) that can be used for making a dynamic management of the cores of a processor in a heterogeneous (software and/or hardware) multicore system. The current solutions are limited by the fact that they don’t make it easy for the user/OS to manage the applications that need a specific set of cores.

Using the Multicore Master Register Configuration makes the programmer’s life easier to write parallel embedded code, letting him to allocate statically or dynamically the core resources, knowing at every step easily what applications are running on what cores. Also, this can be useful for debugging, tracing and in running co-existing operating systems and/or single thread baremetal applications in a multicore embedded environment.

Body

The usage of a MMRC to keep the status for each core in a multicore system will help static and dynamic configuration for cores to be used by co-existing operating systems or single thread baremetal applications in a multicore environment.

The MMRC can be an 8, 16, 32, 64 bit or more addressable registers depending of the complexity of the multicore system.

MMRC [N] is a vector of size N (N = number of the system cores), where each entry is controlling the behavior of a core.

A MMRC item defines the behavior of its corresponding core and can have the following reserved values:

·         -1 (0xFF for up to 254 cores) – core is not used and is in reset or low power mode. It is available to be allocated by other core

·         N – where N is index of the core then the core is running independent code

·         N – where N is different than the index of the core (e.g. M), in this case, the core N allocated core M to its purpose

The MMRC can be set to default values at boot time (initial configuration) and after that the logic can be controlled via 2 blocking (mutual exclusion) operations:

·         Acquire (W) – operation performed by core with the index M, will write value W into the index core N only if the present value is -1 (the core index N – the free core - will be found out by hardware). If the...