Browse Prior Art Database

Acceleration of known WLR wearout mechanisms for Qualification and Reliability Monitoring using thermal gradients of 3D chip layers

IP.com Disclosure Number: IPCOM000240618D
Publication Date: 2015-Feb-12
Document File: 1 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to easily monitor and qualify parts in a three-dimensional (3D) chip by inserting via chains for stress voiding and metal line structures for electromigration in a layer on a product chip.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 01 of 1

Acceleration of known WLR wearout mechanisms for Qualification and Reliability Monitoring using thermal gradients of 3D chip layers

Current Wafer Level Reliability (WLR) failure mechanism stressing is time and resource intensive, requiring specialized tools, wafers (usually test-sites) and processing, which increases turnaround time (TAT) and introduces capacity constraints due to tool availability. In electromigration testing, a specialized oven

with limited capacity and TCA for diced wafers is required for all stressing. Furthermore, specialized wafers with the containing structures must be manufactured. In addition to most stresses taking up to 1000 or more hours, the amount of preparation and resources needed to begin stress is significant.

Fast electromigration is an alternative inline stress that reduces the need for expensive tooling and cycle time, but has not been embraced by the industry and its results are currently not trusted.

This invention solves the issue of needing specialized tooling, while keeping

traditional (non-fast) WLR models intact. In addition, this structure can be used simultaneously for qualification and ongoing reliability monitoring work.

The novel contribution of the invention is a design that places via chains and metal lines used for both stress migration and electromigration on a layer of the three-dimensional (3D) chip. Said chips exhibit a temperature gradient throughout the module and the sandwiched layers can get very hot....