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Method and System for Operating a Scratch Pad Memory in the Context of an Exposed Pipeline

IP.com Disclosure Number: IPCOM000240709D
Publication Date: 2015-Feb-19
Document File: 2 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for operating a scratch pad memory in the context of an exposed pipeline.

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Method and System for Operating a Scratch Pad Memory in the Context of an Exposed Pipeline

Accelerator based processing units require high energy efficiency to achieve future energy demands such as, for example 20MW/EF for exascale computing systems. On-chip caches can boost the performance by keeping the working set data close to the processing unit but are power hungry due to organization and addressing schemes . So there is a need for an energy efficient solution to store the working set by allowing software to spill register contents into a scratch pad memory located local to the processing unit that operates on effective addresses .

Disclosed is a method and system for operating scratch pad memory in the context of an exposed pipeline. The method and system utilizes software for controlling the scratchpad operations in the context of an exposed pipeline . The scratchpad access interface is energy efficient since no address or data queue is needed , nor any effective address to real address mapping logic. Dependency checking is also not needed as the interface structure guarantees a fixed latency access to the scratchpad . A single issue per compute slice interface also enables use of a single shared reader /writer port on the scratchpad array making it more power efficient .

In accordance with the method and system, a set of memory load/store instructions are issued initially to the scratchpad. A per compute slice scratchpad interface is attached to a compute slice load store unit (LSU) and uses the existing LSU effective address generation logic including an update logic but skips the effective to real address mapping. A separate address and data path is wired from the LSU to the scratchpad

with pipeline stages which meet in accordance with time. Scratchpad load/store instructions bypass the effective to real address mapping since the scratchpad is software controlled and thus directly addressable by the effective address for saving power.

Data paths are wired from the scratchpad back to the LSU for load instructions for allowing writes to scalar regis...