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Multi Vt Reduced-Swing Voltage Bitline Generation and Maintenance Circuit for SRAM

IP.com Disclosure Number: IPCOM000240713D
Publication Date: 2015-Feb-19
Document File: 8 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a reduced-swing local bitline keeper/precharge circuit and methodology using a multiplicity of Vt semiconductor devices to be used in SRAM semiconductor applications.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 8

Multi Vt Reduced - SRAM

As technology scales and only quantized device sizes are available, a reduced precharge voltage for local bitlines is becoming required due to SRAM cell stability and power concerns. Additionally, dynamic logic can benefit from reduced swing circuits. This idea addresses both of these issues.

    The idea described here precharges a dynamic node with a simple NFET source follower and then uses an NFET source follower keeper to hold this node high. In this circuit, the keeper used is a higher Vt device which holds the node to the target voltage. Using a lower Vt device for precharge enables better precharge performance and/or less loading with smaller devices. However, using the same Vt level on the precharge devices and keeper devices would provide increased noise immunity and better read performance. Three alternate circuits are included.

    Standard full-swing precharge solution with PFET precharge devices and without keepers is shown in Figure 1 below. This idea uses LVT (low-voltage threshold) NFET devices to precharge the bitlines. The PCHG signal is pulsed so that the precharge lines can quickly be pulled to a reduced power supply voltage. With a pulsed precharge, precharge performance is essential. This reduced voltage is dependent on the Vt value of the LVT NFET. The HVT (high-voltage threshold) NFET keeper then maintains the bitline at an even lower voltage for better power savings. For high-frequency design, this maximizes the evaluate time versus precharge time. For low-power/lower-frequency design, the keeper maintains the bitline state at a lower voltage (dependent on the threshold voltage of the HVT NFET).

-Swing Voltage Bitline Generation and Maintenance Circuit for

Swing Voltage Bitline Generation and Maintenance Circuit for

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Page 02 of 8

Figure 1

    
Figure 2 below represents the relative voltage levels discussed and the relative precharge performance impact if attempting to achieve a 'target' voltage level.

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Page 03 of 8

Figure 2

    
Three possible circuits are included - Circuit #1 is shown in Figure 3 below. In this circuit, a buffer is used in a feedback path to enable or disable HVT...