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Trench Silicide Contact Structure for Improved Semiconductor Device Resistance

IP.com Disclosure Number: IPCOM000240770D
Publication Date: 2015-Feb-27
Document File: 3 page(s) / 124K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a trench silicide contact structure formed on a silicon-on-insulator (SOI) substrate. This structure provides uniform current distribution across the entire Fin Field Effect Transistor (FINFET) width and greatly improves series resistance.

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Trench Silicide Contact Structure for Improved Semiconductor Device Resistance

Series resistance is a factor that limits performance for Fin Field Effect Transistor (FINFET) technology.

A structure is needed to improve the CA/silicide/silicon resistance from contact to the intrinsic semiconductor device.

The novel contribution is a trench silicide contact structure formed on a silicon-on-insulator (SOI) substrate. The trench silicide contact structure abuts the Buried Oxide (BOX) layer. The trench silicide contact structure is used to connect a semiconductor device to Back End of Line (BEOL) layers such as metal lines. The trench silicide contact structure can be formed on planar silicon, silicon fins, planar silicon with epitaxial layers, or silicon fins with epitaxial layers. The semiconductor device can be planar transistor, fin transistor, or passive devices such as resistor, diodes, Silicon-Controlled Rectifiers (SCRs), and capacitors.

A preferred embodiment is for a multi-gate FINFET device with an epitaxial source drain (S/D). Channel currents flow through the surface of the entire silicon fin. Sidewall silicide is formed across the entire silicon thickness in order to evenly distribute the FET current as well as to improve the overall device series resistance.

Figure 1: Novel trench silicide contact structure

Figure 2: Embodiment 1 process steps

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Figure 3: Embodiment 2 process steps

Figure 4: Embodiment 3 process steps

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