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Method and System for Verifying Microprocessor Branch Prediction Logic based on Preloaded Constrained Instruction Streams

IP.com Disclosure Number: IPCOM000240772D
Publication Date: 2015-Feb-27
Document File: 5 page(s) / 126K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for verifying microprocessor branch prediction logic based on preloaded constrained instruction streams.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 41% of the total text.

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Method and System for Verifying Microprocessor Branch Prediction Logic based on Preloaded Constrained Instruction Streams

Branch Prediction is a performance enhancing feature of a pipelined microprocessor

which helps reducing number of cycles required for executing an instruction stream. It is used to dynamically predict presence of branches in instruction streams, direction (taken vs. not-taken) and target address of branch instructions. It allows processing to continue in a predicted path without having to wait for resolution of branch conditions. Branch prediction logic employs one or more Branch Target Buffers (BTB) that are basically arrays that store attributes about branch instructions like address tag, direction (branch history state or BHT) and target address. It is a cache of branch information and is analogous to caches. For highly complex microprocessors that support a variety of branch instructions, the number of attributes that a BTB stores and the circumstances by which they get written or updated increases significantly. Verifying

Branch Prediction logic in simulation is a complex challenge given the tight schedules.

It involves creating scenarios that get the entries in the BTB into certain interesting states and creating streams that contain instructions that make use of the existing BTB entries and get predictions (hits resulting from read) from the BTB and also writes or updates to the BTB based on the outcome of branch instructions. Often it takes several iterations of a particular branch instruction to be fetched and executed for the resulting BTB entry to form in a particular way to potentially create a corner case prediction for subsequent occurrences. This restricts the possibility of finding logic defects early specifically when using random instruction streams which are not constrained based on the BTB contents or history of past instructions.

Disclosed is a method and system for verifying microprocessor branch prediction logic based on preloaded constrained instruction streams. The method and system allows verification of microprocessor branch prediction logic by inserting specific instructions, for both branches and non-branches. The specific instructions are inserted into random instruction streams to form test patterns for verifying the branch prediction logic of a microprocessor. The scheme also allows to define behavior that allows particular instructions to exhibit during dispatch (stall cycles, conditional versus unconditional branch) and in case of branch instructions during address generation (target address, branch wrong target) and resolution (taken vs. not taken, branch wrong direction). The scheme also provides preloading (initialization at beginning of test) entries into the different branch target buffer arrays (BTB) of the hardware being tested to create interesting predictions for instructions in the stream.

In accordance with the method and system, the verification scheme assumes a mi...