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A Method of Reducing Non-volatile Memory Test Time via SoC SRAM Remapping

IP.com Disclosure Number: IPCOM000240775D
Publication Date: 2015-Feb-27
Document File: 3 page(s) / 116K

Publishing Venue

The IP.com Prior Art Database

Abstract

Embedded Non-volatile Memory (NVM) is widely used in current SoC designs. However, NVM needs more test time than most other IPs. This article introduces a method to reduce test time by remapping SoC SRAM for NVM module, which is controlled by a RISC core. The purpose of remapping is to enlarge the memory of the NVM RISC core so that it can hold more test patterns.

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A Method of Reducing Non-volatile Memory Test Time via SoC SRAM Remapping

Abstract

Embedded Non-volatile Memory (NVM) is widely used in current SoC designs.  However, NVM needs more test time than most other IPs. This article introduces a method to reduce test time by remapping SoC SRAM for NVM module, which is controlled by a RISC core. The purpose of remapping is to enlarge the memory of the NVM RISC core so that it can hold more test patterns.

I.                    Introduction

In recent years embedded NVM is more and more popular in microcontroller chips. There are two types of control mechanism, one is state machine based, and another is RISC core based. The RISC core based NVM has advantage that has flexible parameter and algorithm selection, easier bug fix by firmware update. In generally it has a local small SRAM to run its own codes to execute program or erase commands. But the local SRAM might be a bottleneck while executing test patterns, because that the local SRAM has a small size, which cannot contains enough patterns. Now the proposed method is to remap SoC SRAM, and let NVM RISC core directly access SoC SRAM, this removes the memory size limit of local SRAM. A new test flow also introduced to this update.

II.                  Current Test Flow and Memory Architecture

In general, RISC core based NVM module is composed of RISC core, NVM array, Registers and a small local SRAM. The local SRAM is in charge of containing codes for test patterns. NVM array is the module be tested. Register module is the window to receive parameters and commands from SoC interface.

Current test flow:

1.       Enter RAM loader mode and download test pattern codes to NVM local SRAM.

2.       Enter test mode.

3.       Configure NVM registers.

4.       RISC core fetches and execute codes from NVM local SRAM, only contains 1 command.

5.       Save test result and status in NVM module, and send to tester later.

6.       Check if all test commands finished. If not finished, repeat step 1 - 5 ag...