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Automated Wire Tapering of VLSI Interconnect for Enhanced Wire Delay and Slew Performance

IP.com Disclosure Number: IPCOM000240852D
Publication Date: 2015-Mar-06
Document File: 4 page(s) / 57K

Publishing Venue

The IP.com Prior Art Database

Abstract

An automated approach to in-situ non-uniform wire tapering, using real-time extraction of resistor–capacitor (RC) and slew rate (how quickly a circuit's output voltage can change), and tree traversal for arbitrary wire topology is disclosed.

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Automated Wire Tapering of VLSI Interconnect for Enhanced Wire Delay and Slew Performance

Disclosed is an automated approach to in-situ non-uniform wire tapering, using real-time extraction of resistor-capacitor (RC) and slew rate (how quickly a circuit's output voltage can change), and tree traversal for arbitrary wire topology. The disclosed method allows for an automated tool that can reach a solution for one or thousands of nets quickly. This would allow wire tapering on a chip-wide scale productively; enhancing performance and saving a portion of chip power.

Non-uniform wire tapering of metal in a Very-large-scale integration (VLSI) chip can reduce net capacitance and reduce sink slew times, while also reducing dynamic power.

In the past, engineers have performed wire tapering by manual means, but this is tedious and time consuming, and finding an optimal solution manually is difficult. For example, optimizing just one net might take hours, a few score nets would require days or weeks; inhibiting use of this technique on a large scale.

Normally, VLSI interconnect on a given layer is of uniform width. That width might be

the default minimum width for that layer for the manufacturing tolerance, or multiples of the default width, chosen for lower resistance to achieve faster net delay. But wider

widths come at the cost of higher capacitance, which can result in longer net delay and higher far end slews. The optimal solution can be found by using a wider width for the given layer at the source end of the wire, and narrower widths at the receiving end. Iteratively modifying the wire widths while checking the performance (Spice, static timing analysis) can achieve a solution, but is tedious and troublesome if done manually.

For a given segment (a portion of VLSI interconnect long enough for this technique to be effective), the width of the long segment can be narrowed in small portions iteratively, performance checked (delay, sink slew) to see if performance improves, and this process repeated until the performance stops improving. If the segment is several multiples of the default width (i.e. 4x or 3x), the process can proceed by initially narrowing from the widest width down to the next step in width, such as 4x to 3x, or 3x to 2x. Narrowing proceeds from the sink end toward the source end in small steps of

wire length. If while narrowing the widest width and checking timing, the timing metric stops improving and then worsens, the procedure stops; replaces the segment being considered with the new length of narrower wire, and the algorithm can be restarted on the narrow sink-end segment. For example if the 1st narrowing process was from 4x to 3x, now a new iteration process starts to narrow the 3x segment to 2x. The process concludes when the algorithm has narrowed to the default wire width for the given layer, and the timing no longer improves.

The main process for tapering involves a:


Major pass; which manages starting at the...