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Hybrid Cache with Dynamically Allocatable Software Addressable Lines

IP.com Disclosure Number: IPCOM000240882D
Publication Date: 2015-Mar-09
Document File: 1 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that exploits the properties of accelerators to provide efficient local storage. This method dynamically reserves software controlled and Effective Address (EA) addressable private cache lines to enable tight control of performance-critical data in small caches.

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Hybrid Cache with Dynamically Allocatable Software Addressable Lines

Workloads often require additional local memory to run efficiently even for in -memory accelerators with large register files. Normal caches are inefficient in this context because energy efficiency makes the accelerator very sensitive to cache -size, small caches are easily polluted (especially in gather/scatter context), and caches waste energy in streaming data context.

A method is disclosed that provides the capability to dynamically reserve individual cache lines to enable tight control of performance -critical data in small caches. These reserved cache lines are private to the software thread that reserved them and access to these private lines is controlled by the software thread. This eliminates the risk for line eviction of critical data at a bad time and enables local register spilling without congesting the memory crossbar with write-through to memory. These reserved cache lines are also addressed in Effective Address mode , avoiding the translation from effective to real address, thus providing energy efficient operation.

The method provides a special store instruction that enables the privatization of an accessed cache line. A cache line that is to be made private is first evicted if it is already valid and then becomes software managed with direct EA addressing . A private bit for each cache line indicates whether the line is currently private . Private load/store instructions are...