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Defect Free GaAs Growth on Germanium Substrates and Resulting Substrate and Device Structures

IP.com Disclosure Number: IPCOM000240895D
Publication Date: 2015-Mar-10
Document File: 5 page(s) / 105K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure with a graded 98% Silicon Germanium (SiGe) interlayer that addresses the defect density problem with III-V semiconductors.

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Defect Free GaAs Growth on Germanium Substrates and Resulting Substrate and Device Structures

III-V semiconductors are used as channel material for future device nodes. The challenge is the co-integration with silicon. Integrating III-V on silicon substrate is challenging due to the huge lattice constant mismatch between III-V semiconductors and silicon (5.6-6.4 Ang vs. 5.4 Ang for silicon).

One option to circumvent this problem is to start with a Germanium (Ge) wafer, or more feasible a Germanium-on-Insulator (GeOI) wafer produced by wafer bonding. That eliminates the first order on introducing defects due to lattice mismatch. Now, if a process grows Gallium Arsenide (GaAs) onto the "perfect" Ge, there is still a lattice mismatch of 0.1%. (GaAs = 5.65325 A, Ge = 5.658 A). This seemingly little gap does lead to defect formation in the GaAs if grown on the Ge and can lead to surface defects in the order 1e2 to 1e3, which is already too high for device yielding in Complementary Metal Oxide Semiconductor (CMOS) manufacturing.

The novel solution is a structure with a graded 98% Silicon Germanium (SiGe) interlayer that addresses the abovementioned defect density problem.

Embodiment #1: Using a GeOI wafer, certain areas can be optionally recessed through the Ge and the Buried Oxide (BOX) to expose the Si of the handle wafer and Silicon or Si with SiGe can be regrown on those regions.

Figure 1: Start with a Ge substrate or a GeOI wafer

Figure 2: Grow thick relaxed reve...