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A method to find optimal locations for register and its associated test logic

IP.com Disclosure Number: IPCOM000241029D
Publication Date: 2015-Mar-20
Document File: 1 page(s) / 24K

Publishing Venue

The IP.com Prior Art Database

Abstract

This article is related to Electronic Design Automation (EDA) tools, in particular Physical Synthesis, that is used to design high performance VLSI designs. Simple sequential elements such as individual registers/latches may be placed in sub-optimal locations (with respect to timing) if there is a test logic loop. Any existing box movement techniques that do not consider such test logic connections may fail to provide optimal locations. Moving register/latch alone may degrade timing due to test logic being left behind. Developing or enhancing existing techniques to move multiple boxes at the same time may be very significant amount of work or too complex. In this publication, we propose a novel and simple technique to significantly improve locations & timing for such sequential elements.

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A method to find optimal locations for register and its associated test logic
When a register/latch drives a multiplexor (mux) and the mux connects back to the latch at its scan pin input (forming a test logic structure), prior methods which move one box at a time, may not find good locations for the latches. If a primary input (PI) drives a latch & it's test logic which are far away from the PI, such prior methods may only move the latch. In that case the timing from latch to mux may get much worse. If the timing is marked as do not care on this connection then we may still have a long scan connection. This may have a big impact on timing and congestion for high performance ASIC designs with lot of test logic structures.

Here is an outline of the proposed method:

Step 1: Identification:


For each latch with negative timing slack, detect if it drives a mux gate (ignore buffers) and is also driven by the same mux gate.

Let net A be the output net of the mux that drives latch (scan input), and net B be the latch output net that drives the mux (visible timing)

Step 2: Timing mask:
Set a timing "do not care" flag on both A and B (Current flows may be already masking timing on net A) Step 3: Move the objects:
Approach 1: Move register first with a box movement transformation. If successful, move the mux and buffers closer to the register near the new location.

Approach 2: Group register and mux (and any buffers in between) into a big macro object C. Move the C to its opt...