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Method for Extracting NFET to PFET Device Performance Offsets in a CMOS Process

IP.com Disclosure Number: IPCOM000241039D
Publication Date: 2015-Mar-21
Document File: 2 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a circuit for optimizing fast process parameter extraction using a boot-strap pass-gate technique that supports full rail-to-rail transitions for measurement stability as well as eliminating contention between a negative Field Effect Transistor (NFET) and a positive Field Effect Transistor (PFET). In addition, the article presents a circuit for simplifying pass-gate architectures in terms of less area and less wiring congestion.

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Method for Extracting NFET to PFET Device Performance Offsets in a CMOS Process

Dedicated test-chips and/or scribe line (kerf) measurements are insufficient for product monitoring, line centering, and model-to-hardware correlation (MHC) activities. On-chip embedded process monitors are needed to obtain more information about the process from the product dies. These easily measurable structures (present on all chips) can provide several benefits such as:

• Continuous tracking of key process parameters across die, across wafer, and across lots in real product environment

• Product screening and line centering • Correlation of measured data to ASST and statistical timing results
• Chip-level timing models for improved model-to-hardware correlation

On-product structures must meet the following constraints for effective process learning:

• Ease of measurement - preferably frequency based measurements • Parameter separation capability - separate NFET, PFET skew and isolate process space (VT, TOX, Leff) variation
for effective process learning and model generation
• Compact, minimally invasive circuits

A new negative Field Effect Transistor (NFET) to positive Field Effect Transistor (PFET) performance offset Product Screen Ring Oscillator (PSRO) monitor is presented that greatly improves the separability of process parameters for accurate process characterization. The technique uses a single boot-strap passgate between stages that dominate circuit performanc...