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Methods of Dual-Strain Devices on SOI

IP.com Disclosure Number: IPCOM000241041D
Publication Date: 2015-Mar-21
Document File: 3 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a solution that comprises three methods for relaxing the tensile silicon before condensing Germanium into it to provide compressive strain.

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Methods of Dual - -Strain Devices on SOI

Strain Devices on SOI

Starting from tensile-strained silicon (Si), which is required for a negative Field Effect Transistor (nFET), in principle, one may invert the sign of the strain by incorporating larger degrees of Germanium (Ge), which is required for the positive Field Effect Transistor (pFET). A method is needed to provide tensile-strained nFET and compressively strained pFET. Over-doping Ge of has been done, but is unattractive for Band-to-Band (BTB) current. It is preferable to begin to incorporate Ge into unstrained silicon, which then allows the same compressive strain at a lower Ge content.

The novel solution comprises three methods for relaxing the tensile silicon before condensing Ge into it, to provide compressive strain. The methods are:

• Etch fins, then relax by II, then condense to strain • Relax by II, then condense to strain, then etch fins
• Relax by etch, then condense to strain, either before or after gate formation

Figure 1: Post-fin cladding condensation

Figure 2: Pre-fin formation condensation

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Figure 3: Post fin-cut and Post-gate formation condensation

Figure 4: Post fin-cut condensation

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