Browse Prior Art Database

Buffer Circuit for Generating Delay

IP.com Disclosure Number: IPCOM000241057D
Publication Date: 2015-Mar-23
Document File: 4 page(s) / 107K

Publishing Venue

The IP.com Prior Art Database

Abstract

Today’s integrated circuits (IC) are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Noise becomes prominent in lower technology nodes. Expectations from current IC’s are high noise immunity, low power and reduced die size. Though it is impossible to meet all of these, designers still should try to meet all of them to the extent possible so there is no loss in other specifications.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Buffer Circuit for Generating Delay

Today’s integrated circuits (IC) are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.  Noise becomes prominent in lower technology nodes. Expectations from current IC’s are high noise immunity, low power and reduced die size. Though it is impossible to meet all of these, designers still should try to meet all of them to the extent possible so there is no loss in other specifications.

In shrinking technologies, all SoC’s have to work in multi modes and multi corners. So there is a tough challenge to meet setup and hold in all corners. Hold violation closure for a design involves Non-Si Hold closure (due to clock - skew) and Si Hold closure (due to clock and data noise). Non-Si Hold fixing is done by downsizing the existing logic or by putting more hold buffers in the path (primarily of low drive buffers) while the Si-Hold fixing can be done by adding more buffers.

Since delay is reversely proportion to drive strength, a low drive strength cell is chosen for hold fixing. These buffers are normal buffer cell with much less drive strength capability. These buffers have their own limitations. They are more noise prone cells. If there is huge timing violations, a chain of buffers are used and so local density becomes high. Below is comparison between Non-Si and Si Hold profiles in any typical design in the Table 1.

Non-Si and Si Hold comparison Table on a typical design:

 

WNS

TNS

No. of Paths

Non-Si Hold

-0.65  ns

-41.02 ns

340

Si Hold

-1.016 ns

-340.228 ns

1294

Table1. Comparsion between Si/Non-Si hold fixing in any design

Contribution of noise from various elements in noise:

1)    20-25% is from clock noise

2)    50-55% logic data path elements

3)    15-20% is from hold buffers added in the design

Fig. 1 depicts a conventional Buffer design (http://www.ele.uri.edu/research/vlsi-buffer.html) that has been used for hold fixing.

Fig. 1 Conventional Buffer Cell Design

          The conventional buffer design is not able to provide the desired delay needed for hold fixing and if a lower strength buffer needs to be used for more delay then that buffer suffers from noise. So all these shortcomings led us to think of a new buffer design that is capable of meeting hold timing without any impact in area, and having a high delay with the same noise immunity, i.e., a cell with more delay and the same drive strength so that it’s noise immunity also remains the same.

The proposed buffer cell design is shown in Fig. 2.  In the design, transistors Ma and Mb have been added which are ALWAYS ON to provide the necessary required delay without affecting the input capacitance of the cell.  ...