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Glitch-free Clock multiplexer

IP.com Disclosure Number: IPCOM000241121D
Publication Date: 2015-Mar-27
Document File: 3 page(s) / 154K

Publishing Venue

The IP.com Prior Art Database

Abstract

Clock switch between asynchronous or different frequency synchronous clock sources may result glitch on output. Mutual exclusive clock switching between two clocks often involves meta-stability prevention and clock sample each other. It becomes complicated and costly when there are more than two clock sources. In this paper we propose a simple clock switching circuit without circuit increase when the number of clock sources increases.

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Glitch-free Clock multiplexer

Abstract:

Clock switch between asynchronous or different frequency synchronous clock sources may result glitch on output.  Mutual exclusive clock switching between two clocks often involves meta-stability prevention and clock sample each other.  It becomes complicated and costly when there are more than two clock sources.  In this paper we propose a simple clock switching circuit without circuit increase when the number of clock sources increases.

1.   Normal method for multi-source clock switching

The usual method to process more than two clock sources switching to prevent a glitch is using a circuit with "EN" signal" to make each clock source clean enough to be "ORed" together as the final output clock. This circuit becomes larger with an increased number of clock sources.

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2.   Realization Structure

A simple glitch-free clock switching method comprising a direct multiplexer (2~n to 1) plus a clock gating cell using to “gate” the one or more pulses (glitch/glitches) after each switching.  Process the "multiplexed" clock output with only one set of circuit, which simplifies the circuit with no limited number of clock sources.

Below left is a general structure, the requirement is “Gate” signal must be wider than “Select” which mean keep on gating any changing on “Swclk” pass to “CLKOUT” until switching finish.

Below right is an example realization structure with “Gate” generation.   “Gate” will stay low (low effective for ‘G’ end) due to “Select” changing, and “Gate” change to high later after “Select” finish, then glitch on “Swclk” will be prevented pass to output:

                       Figure 1. Clock Mux and example and waveform

With additi...