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Sophisticated Calibration Technique for PLL for Optimized Loop Dynamics

IP.com Disclosure Number: IPCOM000241122D
Publication Date: 2015-Mar-27
Document File: 6 page(s) / 238K

Publishing Venue

The IP.com Prior Art Database

Abstract

A multilevel PLL calibration technique is proposed that tunes the loop parameters for optimised performance. It tunes digital to analog converter (DAC) current to oscillator, voltage to current converter gain and loop filter initial reference voltage. The PLL achieves frequency lock with the best available loop parameters (input controls) across all PVT. If frequency lock is achieved with the best available input controls then the PLL will have a better available control voltage range to achieve phase lock and the PLL performance will be better.

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Sophisticated Calibration Technique for PLL for Optimized Loop Dynamics

Abstract

A multilevel PLL calibration technique is proposed that tunes the loop parameters for optimised performance. It tunes digital to analog converter (DAC) current to oscillator, voltage to current converter gain and loop filter initial reference voltage. The PLL achieves frequency lock with the best available loop parameters (input controls) across all PVT. If frequency lock is achieved with the best available input controls then the PLL will have a better available control voltage range to achieve phase lock and the PLL performance will be better.

Introduction

At lower supply voltage, the dynamic range of the control voltage for PLL operation is quite limited so wide input frequency range and wide output frequency range PLL need proper frequency calibration techniques to reach the desired frequency with the best tuned loop parameters during frequency lock mode. At lower input frequency the bandwidth of the PLL should be decreased.  However, lower PLL bandwidth is also governed by VCO noise and SSCG operation frequency so PLL bandwidth cannot be very low. In a conventional architecture, the PLL does it’s frequency calibration in a single run.  That is, only one control input is varied to achieve frequency lock and once the frequency lock is achieved, there is no detection that it has been achieved with the best available control inputs.

Figure 1 shows the conventional frequency calibration technique. Here frequency calibration using DAC current source is done at:

1)    A fixed reference voltage going as initial voltage to loop filter

2)    A fixed voltage to current converter gain

Only one loop parameter is varied to achieve frequency lock, which may not be the best available control input to achieve the frequency lock.

Figure 1: Conventional frequency calibration architecture

A PLL calibration technique is required that can achieve the desired wide output frequency range and wide input frequency range with the best tuned loop parameters. The proposed technique does multi-level PLL calibration and finds the best available control inputs to achieve the frequency lock.

Proposed Circuit Description

A PLL frequency calibration technique that does multi-level calibration to select the best available input control to achieve the frequency lock is proposed. Figure 2 shows the frequency calibration technique of the proposed architecture. It is a multi-level PLL calibration technique that tunes the following loop parameters for optimised performance of PLL operation.

1)    DAC current source of oscillator

2)    Voltage to current converter gain

3)    Loop capacitor initial reference voltage

Figure 2: Proposed frequency calibration architecture

Figure 3 is a flow chart illustrating the proposed frequency calibration architecture.

Figure 3: Flow chart of Proposed frequency calibration architecture

A fixed reference voltage is applied at loop filter and DAC current sources are varied in b...