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Methods for reducing the error associated with the use pre-scalers in the performance monitoring counters, due to prescale round-off or truncation

IP.com Disclosure Number: IPCOM000241143D
Publication Date: 2015-Mar-31
Document File: 6 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Summary of the present teaching is to reduce the prescale round-off or truncation error by way of reading the MSB and increment the main counter by 1. Another solution for the same is to preload the prescale counter by 50percent of max value the counter can hold so that there would be a carry generated once the number of counts crosses thus reducing the truncation error

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Page 01 of 6

Methods for reducing the error associated with the use pre -scalers in the performance monitoring counters, due to prescale round-off or truncation

Methods for reducing the error associated with the use pre-scalers in the performance monitoring counters, due to prescale round-off or truncation

Introduction

In modern day Processors, many of performance counters are involved in counting major events
These counters are used by different design team during different phases of design and by the end users of the product.

These counters are used extensively in Unit and System level verification coverage, system characterization, capture system performance numbers etc.. To name a few are requests on host bus, acknowledgements on host bus, utilization based data on the physical interface (idle cycles Vs cycles with some information)

In these performance counters, care is taken during design to group specific event bus that needs to be counted for meaningful data interpretation
Also to account for variability in the counts, these counters normally have pre-scalar before the actual counter.

    These counters roll off first to enable counting counted on the main counter
Prescale is a usual approach used in almost all counters to get counter data as per the accuracy needed with the available, limited-size, counters.

Since events from the HW (processor) occur at different frequency, prescale is used to accommodate the total counts in the counter by deciding to measure counts every 16 (4bit prescale) or every 256 (8bit prescale) or 65536 (16bit prescale) or even every 1048576 (20bit prescale)

Using this approach one can count both very-frequently occurring events and very-rarely occurring events using the same counter, but by using different prescale (lower prescale for less-frequently occurring events and higher prescale for very-frequently occurring events)

Reducing the prescale round-off or truncation error. Today with there is no way to reducing the prescale round-off or truncation error other than reading the entire prescale counter value which in most of the cases is not feasible as design would not permit

Explanation

In the existing setup, there are 4levels of prescale as shown above.

When a prescale level of 8bit is chosen, then Counter1 (applies to all other counters) will get counted every 2**8 (256 counts) events by capturing the carry generated
When a prescale level of 20bit is chosen, then the counter1 will get counted every 1million counts.

The events that are in usual performance monitoring unit occurs at different frequency

1


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It is very difficult to fix up a pre-scale to get correct and accurate event count (if a higher-level prescale is used for rarely occurring events), as well as to avoid over flow (if a lower level prescale is chosen for very frequently occurring events)

So each event needs to be carefully monitored by choosing right prescale

Fig1

The main intent is to reduce the prescale round-off or truncation error...