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Method and apparatus to test integrated circuits with reduced number of pins

IP.com Disclosure Number: IPCOM000241181D
Publication Date: 2015-Apr-01
Document File: 6 page(s) / 691K

Publishing Venue

The IP.com Prior Art Database

Related People

Sahil Jain: INVENTOR [+4]

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 32% of the total text.

Page 01 of 6

Cadence Design Systems, Inc.

Inventors: Akhil Garg, Dale Meehl, Sahil Jain

TITLE

Method and apparatus to test integrated circuits with reduced number of pins

PROBLEM AND SOLUTION

test. With some designs having as less as 3 pins to be used for digital test. This application describes a method and apparatus for testing digital chips with as less as 3 pins.

CLK, the response of test can be observed on SO.

The 3 pin test method was implemented for benchmark circuit available from IEEE symposium. Table 1 of the Appendix shows coverage and pattern numbers for the benchmark design.

Table 1 of the Appendix shows the coverage and pattern count for benchmark circuit.

Design Number of Flops Dynamic Faults Static Faults

Pattern Count Coverage Pattern Count Coverage

Benchmark design - I 8808 326 85.37 10 99.58% the viability of the solution.

Fig. 1 of the Appendix shows the block level diagram of three pin test controller. The three pin The SI pin needs to be a dedicated test pin. Additionally, there are two optional pins Test-mode and POR available with the controller. If test-mode is available, (either generated internally on generated through on chip Power-on Reset block. The 3-pin controller requires a definition of max-scan-length to compute the maximum scan shifting capacity of the controller. Let's refer the max shift capacity as 'SL'

The major components of the controller are:

Some ASIC designs have stringent constraints on number of pins that are available for digital

The three pin test requires only three pins for ATPG i.e. Scan In(SI), Scan out(SO) and a clock

port (CLK).The major components of the controller are Finite state machine, counters, reset

mechanism , Test data registers. The proposed solution generates the required test control signals

internally to manage the ASIC test. Thes stimuli is applied to the design through SI and and

The design was successfully implemented and the simulations for all the vectors passed proving

test requires only three pins for ATPG i.e. Scan In(SI), Scan out(SO) and a clock port (CLK).

user chip with some protocols or externally) SI does not be a dedicated test pin. POR can be


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• Two Test Data register to program the testing requirements. Fig 2 of the Appendix shows extended to any number of bits to meet the test requirements.

o A scan TDR to program the shift capabilities and scan protocol.
o A Test TDR to program the test capabilities like stuck-at test generation/delay test

/ reset test generation.


• The controller has two reset mechanisms.

o Figure 3 of the Appendix shows the header protocol used to detect the internal reset generation and digital test initialization.

o In addition, an internal reset can also be generated with user defined signature of number of cycles which can be chosen by user. For example a signature of SI = logic '1' for SL + 10 cycles.

• A Finite State Machine (FSM) is implemented to control the operations of test controller. Fig 4 of the Appendix s...