Browse Prior Art Database

Instance Specific Call-graph Profiling Across HDL and User C Code

IP.com Disclosure Number: IPCOM000241182D
Publication Date: 2015-Apr-01
Document File: 5 page(s) / 129K

Publishing Venue

The IP.com Prior Art Database

Abstract

An essential and important step in designing an Soc is its verification. Simulation based verification is the most commonly used technique to verify and SoC. As the SoC designs are getting larger, the time needed to verify them is also increasing. The verify->debug->verify cycles makes it even more important to reduce the time taken by a verification cycle. In order to decrease verification time, the simulation speed needs to be increased. This invention helps in increasing simulation speed by giving insights into the performance bottlenecks of one or more simulation runs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 27% of the total text.

Page 01 of 5

Cadence Design Systems, Inc.

Inventors: Arnav Kumar Saxena, Sandeep Pagey

TITLE

Instance Specific Call-graph Profiling Across HDL and User C Code

PROBLEM and SOLUTION

state-of-the-art simulator provides a runtime environment which allows interactions among

The need for performance in such an environment is addressed by using a profiling tool to identify bottlenecks in the simulation environment and addressing those bottlenecks. Profiling a simulation run in a complex multi-language environment poses its own challenges. For example, consider a Verilog Task, which can be called from two other tasks.

provide information on time spent in each component and the context in which time is spent. For example shown in Fig 1 of the Appendix, the basic information is time spent in each task.

determining whether to target any of the tasks for optimizations. Understanding the context, in which time is being spent in our tasks, helps in identifying optimizations across different tasks. For example, it might be worthwhile to inline task C in task A, under some set of input parameters. For hardware descriptions of DUT and verification environments, current profiler capabilities do not provide call-graph information.

With the usage of HDLs, a profiler tool is expected to provide information at instance level.

information for each object in the verification environment hierarchy.

The solution of this invention, which will be explained in detail, follows a standard profiling methodology at the core to trigger collection of information. This trigger is at the expiry of a

getting executed when the interrupt was received. The information collected includes:

• the function which was executing

• the class to which this function belongs

• the information about the object in quasi-static hierarchy to which this function belongs in this execution context

For simulation based verification, the verification environment and design can be specified in

different languages. Some common languages are e, SystemVerilog, VHDL, SystemC and C. A

portions specified in various different languages and simulate them together. This invention

helps in increasing simulation speed by giving insights into the performance bottlenecks of one

or more simulation runs.

In order to find performance bottlenecks in such a scenario, a profiling tool is expected to

Additional information is the calling context for time spent in a task. This information helps us in

With advanced methodologies viz. UVM, the verification environment is modeled using

components of pre-defined library classes. A profiler tool is expected to provide profiling

timer interrupt which is set to expire at a regular frequency. On receiving the interrupt, a signal

handler is invoked which proceeds to collect the information of the current context which was



Page 02 of 5


class/object and its call-graph.

instrumentation in the generated code for the verification environment.

Additional book keeping in the tool...