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A data pattern based hardware assisted error injection method to aid in creating error scenarios in functional simulation as well as post silicon validation.

IP.com Disclosure Number: IPCOM000241183D
Publication Date: 2015-Apr-01
Document File: 3 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Related People

Pai G. Raveendra: INVENTOR [+4]

Abstract

Typically, in a design there are hooks and balances to capture and report errors. To verify if these error detection (and correction) and reporting logic is working properly, error scenarios have to be created to stimulate the conditions that cause the required reaction from the design under test. The creation of such error scenarios may not be very straightforward and very difficult to create. Moreover, one would want this error to pop up only occasionally in the entire test to simulate a real live scenario.

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Cadence Design Systems, Inc.

Inventors: Sandeep Brahmadathan, Srinivas Revankar, Pai G. Raveendra functional simulation as well as post silicon validation.

PROBLEM and SOLUTION

error detection (and correction) and reporting logic is working properly, error scenarios have to be created to stimulate the conditions that cause the required reaction from the design under test.

Moreover, one would want this error to pop up only occasionally in the entire test to simulate a real live scenario.

For example, data residing in SRAMs are typically protected by parity. To make sure that the parity consistency checking logic is working properly and to check if the design handles and reports the error properly, one would want the flexibility to inject error randomly and observe the behavior of the hardware as well as the recovery mechanism in software.

Unfortunately, injecting parity errors randomly to make sure all the consistency checkers in the data path behave properly is generally a tedious task. in a pseudo random fashion since typically, the data being passed during test can be (in many cases) under s/w control. under test. the design under test behavior as well as the s/w reaction to these errors. data path protected by parity. There are different stages where the parity check is taking place.

TITLE

A data pattern based hardware assisted error injection method to aid in creating error scenarios in

Typically, in a design there are hooks and balances to capture and report errors. To verify if these

The creation of such error scenarios may not be very straightforward and very difficult to create.

Our solution to the problem mentioned above is a pattern based error injection mechanism. Here,

there is an embedded error injection engine in the design and based on an incoming data pattern,

a trigger is generated which causes the design to self inject a predetermined error (for that

pattern). This way, the design under test's behavior as well as the s/w's behavior can be verified

This mechanism is very useful in post silicon validation and simulation to create the impression

of random parity errors in the data path and the subsequent recovery m...