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Method of Testing Shared Caches/TLB Intervention

IP.com Disclosure Number: IPCOM000241210D
Publication Date: 2015-Apr-03
Document File: 5 page(s) / 267K

Publishing Venue

The IP.com Prior Art Database

Abstract

A validation test environment for testing shared cache and TLB intervention using true sharing of a set of address buckets, where each bucket contains a fixed number of memory addresses, in order to stimulate cache coherence and memory consistency logic, is presented. Tests are run from a main microprocessor(s) and use a loop based algorithm. Each address bucket is treated as a single entity and uses its own reader’s-writer lock to allow concurrent access. For creating additional stress, special instruction(s) called irritators are thrown around each bucket access randomly. The irritators include instructions that directly or indirectly modify cache line states (e.g., cache and TLB management instructions).

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Title

Method of Testing Shared Caches/TLB Intervention

Abstract

A validation test environment for testing shared cache and TLB intervention using true sharing of a set of address buckets, where each bucket contains a fixed number of memory addresses, in order to stimulate cache coherence and memory consistency logic, is presented.  Tests are run from a main microprocessor(s) and use a loop based algorithm.  Each address bucket is treated as a single entity and uses its own reader’s-writer lock to allow concurrent access.  For creating additional stress, special instruction(s) called irritators are thrown around each bucket access randomly.  The irritators include instructions that directly or indirectly modify cache line states (e.g., cache and TLB management instructions).

Background

The usual approach used for stressing true-sharing logic is to run some multi-threaded applications on top of an SMP kernel like Linux.  This doesn’t account for a lot of randomness and there also is not much contention in the system, which limits the number of snoops that can be generated simultaneously due to the nature of the application itself.  Also the execution of this type of application stack is not very tight due to lots of abstraction layers in the software subsystem.  Configurability is also an issue.  There is only so much that can be achieved by this approach.  The validation suit needs to be very tight and highly configurable to be able to hit as much state space transitions as possible in as little time as possible.

In this paper we present a method of grouping fixed and unique sets of addresses into special entities called buckets, where each bucket is protected by a readers’-writer lock (a type of counting semaphore).  We do concurrent accesses (reads/writes/updates) on each of the buckets in a random fashion/order by all the microprocessor cores taking part in the process.  These accesses are inside a runtime/compile-time loop and thus can be iterated any number of times.  This enables us to achieve long runtimes out of simple and compact tests.

Since these tests are run from the main microprocessor(s) and consist mostly of concurrent memory accesses, we are able to achieve various types of machine state transitions inside the entire cache subsystem hierarchy. Similar effects are also reflected in the TLB subsystem due to its similarity with the cache subsystem. The introduction of irritators (cache/TLB management instructions, etc.) acts as a catalyst and may amplify the frequency and/or sequence of cache line state switching thus helping to generate new types of interesting scenarios within the regular machine state transitions achieved via normal true-sharing logic.

The algorithm plays with various cacheable memory addresses making concurrent read/write transactions from various microprocessor cores.  Each access is protected by a reader’s-writer lock so that data is not corrupted and consistency is maintained.  Addres...