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Lane-to-lane skew detection and on-time correction

IP.com Disclosure Number: IPCOM000241221D
Publication Date: 2015-Apr-07
Document File: 2 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Related People

Yonggang Chen: INVENTOR

Abstract

The disclosed invention proposes an architecture using a Bang-bang Phase Detector (BB PD) to detect skew between lanes and using a variable delay line to correct the skew on the fly (in real or near real time). A system including such a configuration can use only one DLL (or PLL) to generate a clock for all lanes. This can avoid having to use separate clock generator for each lane (e.g., either lane based DLL/PLL or phase interpolator), and make the design easier to implement, area efficient and easy to port to different technology. When using a BB PD, most porting can be implemented by RTL, which makes the system easier to design and implement. The disclosed invention is believed to achieve similar or better performance as lane-based clock generator architecture because the disclosed invention can perform inter-lane skew correction in real time during normal operation.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

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Lane-to-lane skew detection and on-time correction

Lane-to-lane skew detection and on-time correction


1. Inventor(s): Yonggang Chen

2. Synaptics Incorporated, San Jose, CA, USA


3. Short Summary

The disclosed invention proposes an architecture using a Bang-bang Phase Detector (BB PD) to detect skew between lanes and using a variable delay line to correct the skew on the fly (in real or near real time). A system including such a configuration can use only one DLL (or PLL) to generate a clock for all lanes. This can avoid having to use separate clock generator for each lane (e.g., either lane based DLL/PLL or phase interpolator), and make the design easier to implement, area efficient and easy to port to different technology. When using a BB PD, most porting can be implemented by RTL, which makes the system easier to design and implement. The disclosed invention is believed to achieve similar or better performance as lane-based clock generator architecture because the disclosed invention can perform inter-lane skew correction in real time during normal operation.

Yonggang Chen

Figure 1 - Two lane example of skew detection and on-time correction using bang bang phase detector and variable delay

Copyright © 2015 Synaptics Incorporated, All Rights Reserved.

Page: 1 of 2

Information contained in this publication is provided as-is, with no express or implied warranties, including any warranty of merchantability, fitness for any particular purpose, or non-infringement. Synaptics Incorporated assumes no liability whatsoever for any use of the information contained herein, including any liability for intellectual property infringement. This publication conveys no express or implied licenses to any intellectual property rights belonging to Synaptics or any other party. Synaptics may, from time to time and at its sole option, update the information contained herein without notice.


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Lane-to-lane skew detection and on-time correction


4. Some Problems Solved

Examples of some of the problems addressed by the invention include:

To deal with inter-lane skew for multiple lane serializer/deserializer, widely used approaches are either use lane based PLL/DLL, or lane-based phase interpolator based on a common PLL/DLL to generate clock for each lane, which requires a complete design and occupy a lot area. The disclosed invention may use one common DLL, and add only bang-bang phase detector (BB PD) along with a variable delay line for each additional lane. The loop for additional lane can be implemented in RTL and the skew between lane can be measured and corrected during...