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SRAM Cut Selection and Decoding for SoC

IP.com Disclosure Number: IPCOM000241238D
Publication Date: 2015-Apr-07
Document File: 8 page(s) / 165K

Publishing Venue

The IP.com Prior Art Database

Abstract

System RAM is an important part of modern day SoCs. The SRAM implementation in any SoC involves mainly three aspects – SRAM cut selection, logical arrangement of these cuts, and the decoding logic required to implement the complete scheme. The first two aspects are based more on the intuition of the designer, while the third step is manual and repetitive across SoCs for the designers. This paper explains how these three aspects of SRAM implementation can be automated, which can in turn help in reducing the design cycle time of the SoC.

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SRAM Cut Selection and Decoding for SoC

Abstract

System RAM is an important part of modern day SoCs. The SRAM implementation in any SoC involves mainly three aspects – SRAM cut selection, logical arrangement of these cuts, and the decoding logic required to implement the complete scheme. The first two aspects are based more on the intuition of the designer, while the third step is manual and repetitive across SoCs for the designers. This paper explains how these three aspects of SRAM implementation can be automated, which can in turn help in reducing the design cycle time of the SoC.

Introduction

System RAM is an important part of most modern SoCs.  SRAM implementation in any SoC has mainly three aspects associated with it:

1.       SRAM cut selection.

2.       The logical arrangement of these SRAM cuts.

3.       The corresponding decoding logic to realize the required memory mapping scheme.

In this paper, we will explain how to automate all the above three aspects.

Let us understand the problem statement first. Earlier, SoC designers used to decide the memory cuts for SRAM to be used across various projects based on the previous experiences and requirements and there was no method to quantify that selection. Also, the decoding logic for the different cuts was generated manually, which was generally error prone and required various iterations during the design cycle that led to increased effort and cycle time. The memory requirements for any SoC keep on changing during the design cycle especially in the initial phase when the definition of the SoC is still being worked out, and to generate the decoding logic for the changed configuration, the designer has to again go through the selection process of the memory chunks and generate the decoding logic. The SRAM cut selection is based on various aspects like power, area or timing. It used to take a lot of time to make the final selection and was still based on the experience of the designer.

Motivation behind automating SRAM implementation flow:

  1. To improve the process of SRAM cut selection, which is entirely based on the cost associated with the various factors (power, area and performance) rather than general feeling or “intuition” of the designer.
  2. To automate the process of generating the decoding logic for the given memory configuration.
  3. To handle the changing memory requirements during the entire cycle of the project. It is a very tedious task for the designer to repeat the process of cut selection and developing the decoding logic for the same.
  4. To eliminate the possibility of occurrence of errors by automating the entire process.
  5. To reduce the overall cycle time by improving the entire methodology of SRAM cut selection and decoding logic generation.

SRAM cut selection and their logical arrangement:

Typically every SoC has a huge amount of SRAM. Memory compilers cannot be used to dump a single cut of such size so smaller cuts are organized together to realize this configuration in SoC.  We can say that...