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PARALLEL VIDEO DECODER FOR MULTI-CORE ARCHITECTURE

IP.com Disclosure Number: IPCOM000241239D
Publication Date: 2015-Apr-07
Document File: 5 page(s) / 171K

Publishing Venue

The IP.com Prior Art Database

Abstract

As High Definition and Ultra High Definition Video become more and more popular, high bit rate video makes computation increasingly complex such that a general processor cannot meet demands. At the same time, existing video decoding methods do not take full advantage of today’s hardware especially multi-core, so an efficient and practical parallel way is needed for video decoder to take full advantage of multi-core hardware. In this paper we present a method by dividing fine task according to the functional module to realize the parallel of video decoder, which can take full advantage of multi-core hardware.

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PARALLEL VIDEO DECODER FOR MULTI-CORE ARCHITECTURE

ABSTRACT

As High Definition and Ultra High Definition Video become more and more popular, high bit rate video makes computation increasingly complex such that a general processor cannot meet demands.  At the same time, existing video decoding methods do not take full advantage of today’s hardware especially multi-core, so an efficient and practical parallel way is needed for video decoder to take full advantage of multi-core hardware.  In this paper we present a method by dividing fine task according to the functional module to realize the parallel of video decoder, which can take full advantage of multi-core hardware.

DESCRIPTION

1.     How is out method organized?

Fig. 1 Frame level HEVC decoder organization

Take high efficiency video coding (HEVC) decoder as an example, HEVC decoder is divided into these threads:

Parser (include Syntax Parsing, Context-based Adaptive Binary Arithmetic Coding (CABAC) Decoding and Output Control), Inverse Discrete Cosine Transformation (IDCT) and Inverse Quantization, Inter prediction, Intra prediction, Boundary, Deblock filter, Sample Adaptive Offset (SAO) filter.

As HEVC decoder contains Luma decoding and two Chromas decoding, so we can further divide these function modules: IDCT and Inverse Quantization, Inter prediction, Intra prediction, Deblock filter and SAO filter into one Luma and two Chromas.

2.     How does our method work?

Fig. 2 Parser thread work flow                            Fig. 3 Task thread work flow

As it is shown in the Fig. 2, parser thread starts first.  It mainly does Syntax Parsing, CABAC decoding, and keep the data in a global buffer, and after it finished this work, it will report its progress, and then it will check the frame’s flag to decide to output or not.

As it is shown in Fig. 3, other task threads start and check two dependencies: one is that whether the parser information it rely on is finish or not, the other is that whether the function module it rely on is finish or not, and after all these tasks finish, the frame’s flag will be assigned to 1.

Fig. 4 dependency between each task (Cur means current CTU block that was processing)

The dependency between each task just as Fig. 4 shows. Take Intra task as an example, current Intra CTU block relies on Top, Top-left, and Left CTU block’s Intra or Inter is finished.  Each task’s dependency is generated by the HEVC spec, the dependency will be checked according to a table which is generated by coordinate (this table can be just like Fig. 4), each task has a table like that, when it finished, it will update the table.

In order to see how our method works on multi-core hardware, we take task: parser, IDCT, Boundary, Intra, Inter and Filter (Deblock or SAO) running on 4 cores as an example (Fig. 5). The independent...