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Method for Instrumenting a Processor Capable of Completing Multiple Groups in a Cycle

IP.com Disclosure Number: IPCOM000241312D
Publication Date: 2015-Apr-15
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for instrumenting a processor capable of completing N instructions in a cycle.

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This is the abbreviated version, containing approximately 55% of the total text.

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Method for Instrumenting a Processor Capable of Completing Multiple Groups in a Cycle

An existing method to instrument a processor is to mark a pseudo-random target group at dispatch and track that group through the pipeline. When the processor attempts to take a sample, it is checked if the target group is the next to complete (NTC) group, and then a sample is taken. In a processor with G possible target groups and wanting S samples, this requires taking approximately G*S samples.

The problem with this design is that it does not support a processor that is capable of completing multiple groups in a cycle. In particular, it will never take a sample on the second group completing in a cycle.

A method is proposed for instrumenting a processor capable of completing N

instructions in a cycle.

In this method, an additional random prediction is made for which group M of the N groups the samples are taken. If the target is between the NTC group and the NTC+M group, then a sample is taken if all groups prior to the target are completing this cycle, and either the target is not completing or the target is NTC+M.

NTC+X is a notation indicating how many groups after the next to complete instruction an instruction is. For instance, in a processor capable of completing two groups in a cycle, this means that an NTC and an NTC+1 group can be completed in that cycle. In general, in a processor implementing up to N completions in a cycle, groups NTC through NTC+(N-1) can complet...