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Method and System for Dynamically Adjusting Resources to Support Multiple Execution Modes

IP.com Disclosure Number: IPCOM000241319D
Publication Date: 2015-Apr-16
Document File: 5 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for dynamically adjusting resources to support multiple execution modes.

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Method and System for Dynamically Adjusting Resources to Support Multiple Execution Modes

As scalar and vector Instruction Set Architecture (ISA) are consolidated for the emerging parallel programming model, a mixture of serial and parallel regions, the processor needs to support multiple execution modes simultaneously . This can be achieved by adding necessary processor resources (i.e. increasing number of registers) required for a new mode to function on top of existing execution modes . However, such approach dedicates and isolates a pool of hardware resource that sits idle if not in use and results in poor processor utilization. Alternatively, the existing processor resources can be re-allocated to support the new mode which results in failure of coexisting with other execution modes (i.e. SMT). There is a need for a method and system that can dynamically adjust processor resources so as to switch between various execution modes.

Disclosed is a method and system for dynamically adjusting resources to support multiple execution modes. The method and system utilizes a compiler for inserting predefined mode switching instructions into application streams so as to allow the mode switching instructions to trigger an exception that invokes supervisor code for reallocating existing resources. In addition, an optimization scheme can be implemented by not allowing the mode switching instructions to cause an exception

when enough resources are available for switching the mode.

In accordance with the method and system, a Mode Status Register can be implemented as a new Special Purpose Register or part of the undefined bits of Machine Status Registers. The Mode Status Register is accessed and maintained initially by an Operating System (OS) in a supervisor mode. Thereafter, through the Mode Status Register, the OS detects available hardware resources for allocating among various workloads. Further, the hardware resources (i.e. regfiles and fetch/dispatch/issue bandwidth) are rationed and arbitrated dynamically for different modes according to the Mode Status Register value as illustrated in the Figure 1.

1


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Figure 1

Consider an exemplary scenario, where a processor supports up to SMT8 mode such as, 8x32 64-bit architected register, 8x64 128-bit architected register, and a fetch, dispatch, and issue width of 8. The Mode Status Register is implemented as a 16 bit register consisting of one enabling bit and one mode indicator bit (thread vs. lane) pair for each of the 8 available hardware threads as illustrated in the Figure 2.

Figure 2

The mode switching instructions are a new set of ISA...