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Stackable BGA Package

IP.com Disclosure Number: IPCOM000241330D
Publication Date: 2015-Apr-17
Document File: 2 page(s) / 234K

Publishing Venue

The IP.com Prior Art Database

Abstract

Package on package is needed for integrating multiple functional dies (e.g. application specific integrated circuit (ASIC) with Memory or system in packaging). However, conventional approaches have long interconnect path between top and bottom dies. Another approach discussed here is a stackable BGA package with direct connections from the center of the bottom die using plated solder balls to the top of the package. Connections are rerouted using second interposer attached on the top of the package. Benefits of the stackable Ball Grid Array package include (1) Top interposer helps to reroute the solder ball connection from the bottom die to different pitch and size; (2) Depending on customer’s need, Substrate 2 can be changed to suit different package geometry such as WLCSP (Wafer Level Chip Scale Package), QFN (Quad Flat No-lead), QFP (Quad Flat Package), etc.; (3) Substrate 2 helps to accommodate discrete components needed for the package, minimizing the customer PCB (printed circuit board) real estate and brings discrete components close to the die.

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Stackable BGA Package

Package on package is needed for integrating multiple functional dies (e.g. application specific integrated circuit (ASIC) with Memory or system in packaging). However, conventional approaches have long interconnect path between top and bottom dies. Another approach discussed here is a stackable BGA package with direct connections from the center of the bottom die using plated solder balls to the top of the package. Connections are rerouted using second interposer attached on the top of the package. Benefits of the stackable Ball Grid Array package include (1) Top interposer helps to reroute the solder ball connection from the bottom die to different pitch and size; (2) Depending on customer’s need, Substrate 2 can be changed to suit different package geometry such as WLCSP (Wafer Level Chip Scale Package), QFN (Quad Flat No-lead), QFP (Quad Flat Package), etc.; (3) Substrate 2 helps to accommodate discrete components needed for the package, minimizing the customer PCB (printed circuit board) real estate and brings discrete components close to the die.

Another benefit of this approach provides shortest interconnection between packages. This approach is suitable for high frequency application because of shorter connection path and minimal discontinuity (e.g. length, shape, etc.) along the signal path. Substrate 1 design is simpler because all top package connections are routed through Substrate 2. Substrate 2 could be a low cost using two layer substra...