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A Constant Voltage Offset Injection Scheme for Differential Successive-Approximation-Register Analog-to-Digital Converter

IP.com Disclosure Number: IPCOM000241333D
Publication Date: 2015-Apr-17
Document File: 3 page(s) / 330K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper discusses the method to inject constant voltage offset to differential successive-approximation-register (SAR) analog-to-digital converter (ADC) with minor change to existing capacitor array found in SAR ADC. The constant voltage offset is fundamental to the stimulus error identification and removal (SEIR) based ADC built-in-self-test (BIST) solution which significantly reduced linearity requirement of test signals. It is proved that this simple modification on differential SAR ADC creates very constant voltage offset without impacting its normal behavior ultimately making its on-chip BIST solution possible.

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A Constant Voltage Offset Injection Scheme for Differential Successive-Approximation-Register Analog-to-Digital Converter

Abstract—This paper discusses the method to inject constant voltage offset to differential successive-approximation-register (SAR) analog-to-digital converter (ADC) with minor change to existing capacitor array found in SAR ADC. The constant voltage offset is fundamental to the stimulus error identification and removal (SEIR) based ADC built-in-self-test (BIST) solution which significantly reduced linearity requirement of test signals. It is proved that this simple modification on differential SAR ADC creates very constant voltage offset without impacting its normal behavior ultimately making its on-chip BIST solution possible.

Keywords— Differential, Successive Approximation Register, Analog to Digital Converter, Voltage Offset, Stimulus Error Identification and Removal, Built-In-Self-Test

                                                                                                                                                                I.     Introduction

Because of the process node advancement, the system-on-chip (SoC) has gained momentum in recent years. More and more analog and mixed-signal blocks are getting integrated into SoCs. The manufacturing cost is continuously driven down by moving to new process node, the test cost however has remained flat. Although structured design-for-test (DFT) technologies like scan based automatic test pattern generation (ATPG) and logic BIST have simplified testing of digital blocks, product test and characterization of analog and mixed-signal blocks are still primarily driven by parameters defined in specification. Analog and mixed-signal block tests in a SoC are proven to be difficult to develop and maintain, and often times requiring expensive tester instruments.

Among many analog and mixed signal blocks, the ADC stands out to be one of the most difficult and costly blocks to test. The static linearity test of ADC requires highly linear test signals to test its differential nonlinearity (DNL) and integral nonlinearity (INL). To address the stringent linearity requirement of test signal, a SEIR based ADC BIST solution is proposed [1]. Assuming constant voltage offset can be injected between two runs on a nonlinear test signal, the nonlinearity of both test signal and ADC under test can be interpolated using least square method. This solution significantly reduced the linearity requirement of test signal, while the constancy of this voltage offset heavily impacts the interpolation accuracy.

 Many circuits have been proposed to create this constant voltage offset. A resistor feedback operational amplifier (Opamp) gain stage is introduced to serve as buffer of test signal while also providing constant offset by switching between different bias voltages [2]. In [3], the author proposed to intentionally introduce mismatches on the differential pair of Opamp that results in constant offset at Opamp’s output. Above approaches involves considerable change or addition to the test signal generator circuit while the performance is not e...