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Method of Enhanced Channel Strain using Suspended Source/Drain FinFETs

IP.com Disclosure Number: IPCOM000241413D
Publication Date: 2015-Apr-24
Document File: 2 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to increase uniaxial strain in the channel of the fin Field Effect Transistors (finFETs). The approach uses a small amount of suspension in the source drain (S/D) regions to relax the strain in the S/D and transfer the force through volume expansion of the already-compressed material to the channel.

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/Drain FinFETs

Drain FinFETs

The application of high levels of strain to three -dimensional (3D) structures such as fin Field Effect Transistors (finFETs) is challenging. Common methods such as embedded source drain (S/D) usually fail, especially at more tightly contacted gate pitches.

Substrate strain engineering may be a practical approach; however, the amount of strain may not be sufficient due to several factors , such as restrictions for the epitaxial critical thickness.

Method of Enhanced Channel Strain using Suspended Source /

A method is needed to further boost the strain in the channel .

The novel solution is additive strain induction in the channel of strained finFETs (i.e. compressively strained-Silicon Germanium (SiGe) or III-V) on bulk or insulator using suspended source and drain. With a small amount of suspension in the S /D regions, one can relax the strain in the S/D and transfer the force due to volume expansion of the already-compressed material to the channel. This increases uniaxial strain in the channel of the FinFET.

Figure 1: Fin, Gate, Spacer, and Dummy Oxide Stressor Formation

• Fin material can be either compressively strained-SiGe, Ge or III-V

• Material B can be any insulator (such as SiO2, HfO2, InAlAs, etc.) or a semiconductor for the case of bulk finFET

Figure 2: S/D Suspension, Dummy Spacer Removal

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Figure 3: Embodiment: Compressive Uniaxial Strained-Semiconductor

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