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A Unified Scalar and SIMD Instruction Set Architecture: Repurposing a Scalar Instruction Set for SIMD Instruction via Mode-Sensitive Semantics

IP.com Disclosure Number: IPCOM000241485D
Publication Date: 2015-May-05
Document File: 3 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a unified scalar/Single-Instruction-Multiple-Data (SIMD) Instruction Set Architecture (ISA) with a design based on a conventional scalar ISA (i.e. baseline ISA), plus a few new instructions. The core idea is to design a single ISA that can express both scalar and SIMD semantics depending on the execution mode of the instruction.

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A Unified Scalar and SIMD Instruction Set Architecture : : Instruction Set for SIMD Instruction via Mode -

Modern processors with Single-Instruction-Multiple-Data (SIMD) extensions often provide two sets of Instruction Set Architectures (ISA), one for non-SIMD instructions (scalar ISA), and one for SIMD instructions (SIMD ISA). There are two major limitations of using separate Scalar and SIMD ISAs.

The first limitation is an inefficient use of opcode space . When defining an SIMD ISA, ideally, the user should define one SIMD instruction for each scalar instruction . However, this would almost double the size of an ISA. Furthermore, an existing SIMD ISA has the width of the vectors on which it directly operates encoded in the instruction (e.g., AVX for 256-bit vectors and AVX-512 for 512-bit vectors). When a new generation of SIMD extension expands the width of the vectors on which it operates , another new set of SIMD instructions must be defined in the ISA .

The second limitation is the less-rich SIMD ISA semantics. Sometimes, in order to preserve opcode space (e.g., for fixed-length ISAs such as Power ISA where instructions can only be 4-byte long), the SIMD ISA is often reduced to cover only a subset of a scalar ISA. For example, Power ISA SIMD memory access instructions support only a subset of the addressing modes supported by Power scalar ISA .

The novel contribution is a unified scalar/SIMD ISA with a design based on a conventional scalar ISA (i.e. baseline ISA), plus a few new instructions. The core idea is to design a single ISA that can express both scalar and SIMD semantics depending on the execution mode of the instruction. For this unified ISA, the ISA is based on a conventional scalar ISA plus a few new instructions. The ISA has two types of semantics, scalar and SIMD, which are used according to the execution mode (i.e. lane-mode or thread-mode, below), which operates on two sets of register files.

Two execution modes are defined for a unified scalar /SIMD ISA:


• Thread mode: under this mode, all baseline ISA instructions behave the same as defined in the baseline ISA. In thread mode, all baseline instructions operate on thread registers.


• Lane mode: some instructions keep scalar semantics (called thread instructions),

while others have SIMD semantics (called...