Browse Prior Art Database

Method and System for Enabling Constraint Based Parent Whitespace Sharing Towards Intra-Block Design Closure

IP.com Disclosure Number: IPCOM000241508D
Publication Date: 2015-May-07
Document File: 5 page(s) / 175K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for enabling an intelligent, need based, parent level whitespace sharing across parent and child blocks. A contract scheme is used to reserve segments of the whitespace channel by parent (unit buffers, latch-bank etc.) or child blocks (localized design expansion).

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 5

Method and System for Enabling Constraint Based Parent Whitespace Sharing Towards Intra-Block Design Closure

In modern System on Chip (SOC) implementation, a hierarchical design approach is followed where a parent hierarchy consists of a number of child blocks such as, but not limited to, synthesized, custom IP, other special blocks and there is whitespace in between. Typically, the whitespace is used to plan parent hierarchy wiring resources as

well as to place buffers, latch-banks, level shifters or other special cells (decap, fillers etc.). The total whitespace budget at parent hierarchy can become a significant percentage of parent area and mostly placement utilization percentage will be on a lower side. Therefore there is a need to manage the unutilized whitespace more optimally to cater to selective area needs of child hierarchy and thus leading to overall compact implementation / whitespace reduction.

Disclosed is a method and system for enabling an intelligent, need based, parent level

whitespace sharing across parent and child blocks.

The method and system utilizes a placement and routing contract scheme in order to ensure that no conflicts are created because of sharing between participating blocks/parent. Two level placement boundaries are given to all child blocks between

which additional placement and routing contracts are in force. The positioning of ports of child blocks is restricted within inner placement boundary in order to avoid interference with parent level wiring plans. Global signal distributions (clock, power, reset) are then planned to cover the shared whitespace. Further, intra-block synthesis as well as power and reset are allowed to make use of the additional area resource but

with additional design constraints.

FIG. 1 is an Illustration of a design where child-1 and child-2 have localized design issues (timing/congestion/placement density near boundary) in accordance with the method and system disclosed herein.

1


Page 02 of 5

Figure 1

FIG. 2 illustrates a median line based expanded region in accordance with an embodiment of the method and system disclosed herein.

Figure 2

In accordance with FIG. 2, the whitespace can be used selectively by one child block if that is not used by a parent or other child blocks in same vicinity. The entire parent

whitespace is brought under a contract scheme and once used by one block or parent,

2


Page 03 of 5

the whitespace is tagged with a corresp...